公开(公告)号：WO2013077929A3

公开(公告)日：2013-08-15

申请号：PCT/US2012055061

申请日：2012-09-13

Applicant: IBM ,  FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/00

CPC classification number: G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

Abstract translation: 随机固有芯片ID生成采用保留失败签名。 使用测试设置生成第一和第二ID，第一设置比第二设置更严格，在包括第二ID比特串290的第一ID比特串275中创建更多失败。保留暂停时间控制保留失败次数，调整 由BIST引擎625执行，其中失败编号803,920满足预定的失败目标。 验证确认第一个ID是否包含第二个ID位串，该ID是用于认证的ID。 通过具有中间条件的第三ID来启用认证，使得第一ID包括第三ID位串，并且第三ID包括第二ID位串。 中间条件包括用于消除第一和第二ID边界附近的位不稳定问题的保护带。 中间条件在每次ID读取操作时发生变化，从而导致更安全的识别。

公开(公告)号：WO2008109654A3

公开(公告)日：2008-11-06

申请号：PCT/US2008055875

申请日：2008-03-03

Applicant: IBM ,  CESTERO ALBERTO ,  PARK BYEONGJU ,  SAFRAN JOHN M

Inventor： CESTERO ALBERTO ,  PARK BYEONGJU ,  SAFRAN JOHN M

IPC: H01L21/82 ,  H01L21/326

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antifuse (100) having a link (125) including a region (150) of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode (120) into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode (120) and anode (110) are preferably shaped to control regions from which and to which material is electrically migrated After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures

Abstract translation: 具有包括非硅化半导体材料的区域（150）的链路（125）的反熔丝（100）可以以降低的电压和电流被编程，并且通过金属或硅化物从阴极（120）的电迁移到区域 的非硅化半导体材料以形成具有降低的体积电阻的合金。 阴极（120）和阳极（110）优选地被成形为控制从哪个材料和哪些材料电迁移的区域。在编程之后，材料的额外的电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上

公开(公告)号：CA2852883A1

公开(公告)日：2013-05-30

申请号：CA2852883

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROSENBLATT SAMI ,  ROBSON NORMAN W

IPC: G11C29/00 ,  G06F21/00

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：DE112012004439T5

公开(公告)日：2014-07-17

申请号：DE112012004439

申请日：2012-09-13

Applicant: IBM

Inventor： CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  ROBSON NORMAN W ,  ROSENBLATT SAMI ,  FAINSTEIN DANIEL J ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/00

Abstract: Eine Erzeugung einer zufälligen intrinsischen Chip-ID verwendet eine Speicherfehlersignatur. Eine 1. und eine 2. ID werden unter Verwendung von Testeinstellungen erzeugt, wobei eine 1. Einstellung restriktiver als die 2. ist und in der ersten ID-Bitzeichenkette 275, welche die 2. ID-Bitzeichenkette 290 enthält, mehr Fehler erzeugt werden. Eine Speicherpausenzeit-Steuerung steuert eingestellt durch eine BIST-Engine 625 die Anzahl von Speicherfehlern, wobei die Fehleranzahlen 803, 920 ein vorgegebenes Fehlerziel erfüllen. Eine Überprüfung bestätigt, ob die 1. ID die 2. ID-Bitzeichenkette enthält, wobei es sich bei der ID um die für die Authentifizierung verwendete handelt. Die Authentifizierung wird durch eine 3. ID mit einer derartigen Zwischenbedingung ermöglicht, dass die 1. ID die 3. ID-Bitzeichenkette enthält und die 3. ID die 2. ID-Bitzeichenkette enthält. Die Zwischenbedingung enthält ein Wächterband, um ein Bitinstabilitätsproblem nahe der 1. und 2. ID-Grenze zu beseitigen. Die Zwischenbedingung wird bei jedem ID-Lesevorgang geändert, was zu einer sichereren Identifikation führt.

公开(公告)号：IN2203CHN2014A

公开(公告)日：2015-06-12

申请号：IN2203CHN2014

申请日：2014-03-21

Applicant: IBM

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROBSON NORMAN W ,  ROSENBLATT SAMI

IPC: G11C29/00 ,  G06F21/00

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails adjusted by a BIST engine 625 wherein the fail numbers 803 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation resulting in a more secure identification.

公开(公告)号：GB2508761B

公开(公告)日：2014-11-19

申请号：GB201404456

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/44 ,  G06F21/73

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：GB2508761A

公开(公告)日：2014-06-11

申请号：GB201404456

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/44 ,  G06F21/73

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.