公开(公告)号：JPH0832414A

公开(公告)日：1996-02-02

申请号：JP15135095

申请日：1995-06-19

Applicant: IBM

Inventor： CHII RIYAN CHIEN

IPC: G06F11/22 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3562

Abstract: PURPOSE: To perform an operation by a single phase clock by providing master and slave stages and constituting a device provided with a master segment and a slave segment by the respective master and slave stages. CONSTITUTION: A master/slave latch system 100 is provided with a master latch part 102 and a slave latch part 104. A logical part 106 supplies signals to input 108 and complement input 110 and both of the input are electrically connected to the master latch part 102. The master latch part 102 is provided with output 112 and complement output 114 and both of the output are inputted to the slave latch part 104. The slave latch part 104 is provided with the output 116 and the complement output 118 and they indicate the system output of the master/slave latch system 100.

公开(公告)号：JPH03190426A

公开(公告)日：1991-08-20

申请号：JP31819090

申请日：1990-11-26

Applicant: IBM

Inventor： SAN HOO DON ,  CHII RIYAN CHIEN ,  YUN JIYON SHIN

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H03K17/04 ,  H03K17/567 ,  H03K19/08

Abstract: PURPOSE: To avoid a voltage drop between an emitter and a collector by using a horizontal bipolar transistor having a base defined by the gate of a polycrystalline silicon. CONSTITUTION: A horizontal gate-emphasized PNP transistor(TR) 31 is formed in a BiCMOS integrated circuit together with a longitudinal NPN TR. When an input 29 is a low level, the base connection of the TR 31 is gated by the operation of a P-channel device 33 and turned to a conductive state. At the time, the base device 31 conducts a current and holds a gate at low potential and voltage can be completely pulled up to a level Vdd. When the input state of an inverter is in a reverse state, a high level signal gates the device 34 at an on state, a collector is almost held at Vss and a P-channel device 32 connects its base and emitter together to turn the device to a non-conductive state. Consequently, the function of a MOS FET can be obtained and voltage drop between the collector and emitter can be avoided.