公开(公告)号：JPH05166375A

公开(公告)日：1993-07-02

申请号：JP8872592

申请日：1992-04-09

Applicant: IBM

Inventor： SAN HOO DON ,  YUN JIYON SHIN

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/401

Abstract: PURPOSE: To obtain a memory cell, having a smallest silicon occupying area and high reliability by forming a double port memory by six transistors(TR) and providing a power source voltage line to supply a voltage at a prescribed intermediate level as well. CONSTITUTION: This memory cell is constituted of the six TRs of p-type TRs 28 and 34, controlled by word cables 44, 46 and p-type TRs 20, 24, 22 and 26 forming FF to be supplied with a power source voltage VC through a power source able 50. At the time of writing 1 in a port A in a state where a node X is 0, in advance to the writing, a voltage VC is dropped by not more than 50% to be the intermediate level. Then the conductive state of TR 24 is lowered by a node Y, to raise the potential of the node X. TR 26 comes into a double conductive state to further lower the potential of the node Y, and TR 24 becomes a non-conductive state to write data 1 by a stable flip operation. Similarly, using six TRs and high reliability using six TRs, asynchronous access is satisfactorily executed between ports A and B to make SAM of the smallest silicon area.

公开(公告)号：JPH03190426A

公开(公告)日：1991-08-20

申请号：JP31819090

申请日：1990-11-26

Applicant: IBM

Inventor： SAN HOO DON ,  CHII RIYAN CHIEN ,  YUN JIYON SHIN

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H03K17/04 ,  H03K17/567 ,  H03K19/08

Abstract: PURPOSE: To avoid a voltage drop between an emitter and a collector by using a horizontal bipolar transistor having a base defined by the gate of a polycrystalline silicon. CONSTITUTION: A horizontal gate-emphasized PNP transistor(TR) 31 is formed in a BiCMOS integrated circuit together with a longitudinal NPN TR. When an input 29 is a low level, the base connection of the TR 31 is gated by the operation of a P-channel device 33 and turned to a conductive state. At the time, the base device 31 conducts a current and holds a gate at low potential and voltage can be completely pulled up to a level Vdd. When the input state of an inverter is in a reverse state, a high level signal gates the device 34 at an on state, a collector is almost held at Vss and a P-channel device 32 connects its base and emitter together to turn the device to a non-conductive state. Consequently, the function of a MOS FET can be obtained and voltage drop between the collector and emitter can be avoided.