公开(公告)号：DE2346525A1

公开(公告)日：1974-05-02

申请号：DE2346525

申请日：1973-09-15

Applicant: IBM

Inventor： AHEARN THOMAS PAUL ,  CAPOWSKI ROBERT STANLEY ,  CHRISTENSEN NEAL TAYLOR ,  GANNON PATRICK MELVIN ,  LEE ERLIN EARL ,  LIPTAY JOHN STEHPEN

IPC: G06F12/10 ,  G06F13/06 ,  G06F9/18

Abstract: This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same addresses over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. Each translation retained by the DLAT is identified by an identifier (ID) that signifies the set of tables used in that translation. This identifier is compared with an identifier generated for the currently requested virtual address. If these identifiers match and the virtual address retained in the DLAT matches the currently requested virtual address, the translation stored in the DLAT may be used. If the identifiers or virtual address don't match, a new translation must be performed using the set of conversion tables associated with the currently requested address.

公开(公告)号：DE3066708D1

公开(公告)日：1984-03-29

申请号：DE3066708

申请日：1980-10-15

Applicant: IBM

Inventor： CHRISTENSEN NEAL TAYLOR ,  VAN LOO WILLIAM CHARLES ,  WERNER ROBERT HELMUT ,  WETZEL JOSEPH ALBERT ,  ZEITLER JR

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16 ,  G06F15/177 ,  G06F13/00 ,  G06F3/04

Abstract: For increased flexibility and efficiency of handling I/O interrupt requests (I/O IR's) in a multiprocessor system having a system controller (SC, 22), processors (CP 20, 21) shared main storage (23) and in I/O processor (IOP in 24), the IOP inserts I/O IR entries onto the queues in MS in accordance with the type of interrupt which entries are only removed by the CPs, after their selection by the controller (SC) for execution of an appropriate interruption handling program. Bit positions in an I/O IR pending register (46) in the SC are respectively assigned to the I/O IR queues in MS, and their order determines queue priority for CP handling. An I/O IR sets a corresponding bit position in register (46) an controls the corresponding queue entry. A broadcast bus (11) connects the bit positions of the pending register to each of the CPs.