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公开(公告)号：DE69522267T2
公开(公告)日：2002-06-13
申请号：DE69522267
申请日：1995-02-03
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , CAPOWSKI ROBERT STANLEY , CASPER DANIEL FRANCIS , JORDAN RICHARD CARROLL , LAVIOLA WILLIAM CONSTANTINO
Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
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公开(公告)号：DE69522267D1
公开(公告)日：2001-09-27
申请号：DE69522267
申请日：1995-02-03
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , CAPOWSKI ROBERT STANLEY , CASPER DANIEL FRANCIS , JORDAN RICHARD CARROLL , LAVIOLA WILLIAM CONSTANTINO
Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
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公开(公告)号：CA2150744A1
公开(公告)日：1995-12-18
申请号：CA2150744
申请日：1995-06-01
Applicant: IBM
Inventor： FERRAIOLO FRANK DAVID , CAPOWSKI ROBERT STANLEY , CASPER DANIEL FRANCIS , JORDAN RICHARD CARROLL , LAVIOLA WILLIAM CONSTANTINO
Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
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公开(公告)号：DE69326573T2
公开(公告)日：2000-04-27
申请号：DE69326573
申请日：1993-01-21
Applicant: IBM
Inventor： BARTOW NEIL GEORGE , BROWN PAUL JOSEPH , CAPOWSKI ROBERT STANLEY , FASANO LOUIS THOMAS , GREGG THOMAS ANTHONY , SALYER GREGORY , SUGRUE PATRICK JOHN , WESTCOTT DOUGLAS WAYNE , ZEYAK VINCENT PAUL
Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.
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公开(公告)号：DE69326573D1
公开(公告)日：1999-11-04
申请号：DE69326573
申请日：1993-01-21
Applicant: IBM
Inventor： BARTOW NEIL GEORGE , BROWN PAUL JOSEPH , CAPOWSKI ROBERT STANLEY , FASANO LOUIS THOMAS , GREGG THOMAS ANTHONY , SALYER GREGORY , SUGRUE PATRICK JOHN , WESTCOTT DOUGLAS WAYNE , ZEYAK VINCENT PAUL
Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.
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Patent Agency Ranking
公开(公告)号：DE2346525A1
公开(公告)日：1974-05-02
申请号：DE2346525
申请日：1973-09-15
Applicant: IBM
Inventor： AHEARN THOMAS PAUL , CAPOWSKI ROBERT STANLEY , CHRISTENSEN NEAL TAYLOR , GANNON PATRICK MELVIN , LEE ERLIN EARL , LIPTAY JOHN STEHPEN
Abstract: This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same addresses over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. Each translation retained by the DLAT is identified by an identifier (ID) that signifies the set of tables used in that translation. This identifier is compared with an identifier generated for the currently requested virtual address. If these identifiers match and the virtual address retained in the DLAT matches the currently requested virtual address, the translation stored in the DLAT may be used. If the identifiers or virtual address don't match, a new translation must be performed using the set of conversion tables associated with the currently requested address.
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公开(公告)号：DE69331449T2
公开(公告)日：2002-09-26
申请号：DE69331449
申请日：1993-02-12
Applicant: IBM
Inventor： BARTOW NIEL GEORGE , BROWN PAUL JOSEPH , CAPOWSKI ROBERT STANLEY , FASANO LOUIS THOMAS , CREGG THOMAS ANTHONY , SALYER GREGORY , WESTCOTT DOUGLAS WAYNE
Abstract: Buffers 54,58 are provided in two elements 52,56 between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being cancelled.
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公开(公告)号：AT212136T
公开(公告)日：2002-02-15
申请号：AT93301037
申请日：1993-02-12
Applicant: IBM
Inventor： BARTOW NIEL GEORGE , BROWN PAUL JOSEPH , CAPOWSKI ROBERT STANLEY , FASANO LOUIS THOMAS , CREGG THOMAS ANTHONY , SALYER GREGORY , WESTCOTT DOUGLAS WAYNE
Abstract: Buffers 54,58 are provided in two elements 52,56 between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being cancelled.
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公开(公告)号：CA2082078C
公开(公告)日：1996-11-19
申请号：CA2082078
申请日：1992-11-04
Applicant: IBM
Inventor： BARTOW NEIL GEORGE , CAPOWSKI ROBERT STANLEY , FASANO LOUIS THOMAS , GREGG THOMAS ANTHONY , SALYER GREGORY , WESTCOTT DOUGLAS WAYNE
Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.
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公开(公告)号：CH626735A5
公开(公告)日：1981-11-30
申请号：CH240178
申请日：1978-03-06
Applicant: IBM
Abstract: The Channel Bus Controller (CBC) transfers information between groups of input/output channels and processor storage. Storage receives or dispenses two data words per access operation. Interfaces for transfers from the channel groups to the CBC are advantageously one word wide; since each output (fetch) request consists of a single request word. Information sent by each group is assembled into three-word units (a request word and zero, one or two data words) in a respective channel bus assembly register (CBAR). The assembled unit is passed from the CBAR to a respective area of an In Buffer array and from that array to storage. Zero filler words are inserted into unused data word positions. A channel request may be tagged to designate a transfer of four data words. If the transfer is an input the four data words are sent to the CBC with a single request word. The third and fourth data words are written in the CBAR over the first and second data words as (or after) the unit formed by the request and first and second data words is advanced to the In Buffer. The same request and the third and fourth data words are transferred as a second unit from the CBAR to the In Buffer. The low order bit in the address part of the request is inverted by the CBC to designate the "next" storage address. This saves time by eliminating a request unit transfer from the source channel group. Request transfers from a group are permitted when a vacancy exists either in the respective CBAR or in a respective area of the In Buffer. Outputs from storage (acknowledgments of data inputs and fetched/output data) are returned to the respective channel group via a respective area of an Out Buffer array. Returns to a group are ordered in the input sequence of respective requests to the CBC although the requests may be applied to storage in another sequence. Tags generated by the CBC are used to maintain the correct output order without delaying evacuation of the In Buffer. The area partitioning of the in and out buffer arrays provides balanced group access to storage and simplifies handling of group traffic. Channel identity information in the request words is looped through the buffer arrays and returned to the channel groups with respective outputs. This permits the CBC (and storage) to ignore channel origins of group traffic and thereby further simplifies handling of traffic.
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