3.
    发明专利
    未知

    公开(公告)号:DE69022872D1

    公开(公告)日:1995-11-16

    申请号:DE69022872

    申请日:1990-02-12

    Applicant: IBM

    Abstract: A bus-to-bus adapter (20) is provided for coupling the input/output bus of a first data processor (21) to the input/output bus of a second and different type of data processor (22). The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit (34) and control logic (39) for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.

    4.
    发明专利
    未知

    公开(公告)号:DE69718716T2

    公开(公告)日:2003-09-18

    申请号:DE69718716

    申请日:1997-06-11

    Applicant: IBM

    Abstract: An calibration apparatus operates in multiple calibration modes of a multi-mode information storage system such as an optical disk drive to calibrate the drive in the multiple write modes. An event processing and measurement circuit is configurable in multiple configurations that each correspond to a different calibration measurement. Each configuration concurrently measures one or more parameters of readback data written to an optical disk by the optical disk drive operating in a particular write mode. A qualification circuit selects valid measurements for two different parameters or for two different qualification of the same parameter. A summation circuit sums valid measurements of each parameter measured and counts the number of measurements summed for each parameter. The calibration apparatus calculates average values for the measured parameters from the sums and counts, and then calibrates the multi-mode optical disk drive for its current write mode based on the average values.

    5.
    发明专利
    未知

    公开(公告)号:DE69718716D1

    公开(公告)日:2003-03-06

    申请号:DE69718716

    申请日:1997-06-11

    Applicant: IBM

    Abstract: An calibration apparatus operates in multiple calibration modes of a multi-mode information storage system such as an optical disk drive to calibrate the drive in the multiple write modes. An event processing and measurement circuit is configurable in multiple configurations that each correspond to a different calibration measurement. Each configuration concurrently measures one or more parameters of readback data written to an optical disk by the optical disk drive operating in a particular write mode. A qualification circuit selects valid measurements for two different parameters or for two different qualification of the same parameter. A summation circuit sums valid measurements of each parameter measured and counts the number of measurements summed for each parameter. The calibration apparatus calculates average values for the measured parameters from the sums and counts, and then calibrates the multi-mode optical disk drive for its current write mode based on the average values.

    6.
    发明专利
    未知

    公开(公告)号:DE69022872T2

    公开(公告)日:1996-06-13

    申请号:DE69022872

    申请日:1990-02-12

    Applicant: IBM

    Abstract: A bus-to-bus adapter (20) is provided for coupling the input/output bus of a first data processor (21) to the input/output bus of a second and different type of data processor (22). The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit (34) and control logic (39) for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.

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