-
公开(公告)号：DE3485205D1
公开(公告)日：1991-11-28
申请号：DE3485205
申请日：1984-08-08
Applicant: IBM
Inventor： BUONOMO JOSEPH PATRICK , HOUGHTALEN STEVEN RAY , LOSINGER RAYMOND ELLISON , VALASHINAS JAMES WILLIAM
Abstract: The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches (32, 34) that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor (12), a secondary microprocessor (14), off-chip control storage (26) belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage (24). The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines (48, 50) responsive to the particular microprocessor action being taken. When set, the instruction override latch directs all expected primary processor main storage instruction fetches to control store. When set, the operand override latch directs all expected primary processor main storage operand accesses to control store. As appropriate for instruction execution, either one or both of the the primary or secondary microprocessors can thereby be transparently latched to main or control storage.
-
公开(公告)号：DE69022872T2
公开(公告)日：1996-06-13
申请号：DE69022872
申请日：1990-02-12
Applicant: IBM
IPC: G06F15/16 , G06F13/38 , G06F13/40 , G06F15/173
Abstract: A bus-to-bus adapter (20) is provided for coupling the input/output bus of a first data processor (21) to the input/output bus of a second and different type of data processor (22). The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit (34) and control logic (39) for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.
-
公开(公告)号：DE69022872D1
公开(公告)日：1995-11-16
申请号：DE69022872
申请日：1990-02-12
Applicant: IBM
IPC: G06F15/16 , G06F13/38 , G06F13/40 , G06F15/173
Abstract: A bus-to-bus adapter (20) is provided for coupling the input/output bus of a first data processor (21) to the input/output bus of a second and different type of data processor (22). The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit (34) and control logic (39) for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.
-
公开(公告)号：BR8301430A
公开(公告)日：1983-11-29
申请号：BR8301430
申请日：1983-03-21
Applicant: IBM
Inventor： AGNEW PALMER WRIGHT , BUONOMO JOSEPH PATRICK , HOUGHTALEN STEVEN RAY , KELLERMAN ANNE SHEILA , LOSINGER RAYMOND ELLISON , VALASHINAS JAMES WILLIAM
Abstract: Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. The mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.For each subset of the instructions that requires high performance, the corresponding microprocessor chip contains the data flow path and all elements, including registers, necessary for the execution of that subset as well as the microcode that controls execution. In some applications, a subset of the instructions that does not require high performance is implemented with a critical path that crosses several chip boundaries and is, therefore, considerably slower. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is ecomonically feasible to have several copies of a complex data flow and control store mechanism.
-
-
-
Search Results
4
records
(took 0.016 seconds)
