公开(公告)号：US6278339B2

公开(公告)日：2001-08-21

申请号：US73567900

申请日：2000-12-13

Applicant: IBM

Inventor： ABADEER WAGDI W ,  CONNOR JOHN ,  HANSEN PATRICK R

IPC: H04L25/02 ,  H03H7/38 ,  H03H7/40

CPC classification number: H04L25/0278

Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

公开(公告)号：JPH08328964A

公开(公告)日：1996-12-13

申请号：JP12731896

申请日：1996-05-22

Applicant: IBM

Inventor： ADAMS ROBERT DEAN ,  CONNOR JOHN ,  KOCH GARRETT STEPHEN ,  TERNULLO LUIGI JR

IPC: G06F12/16 ,  G11C29/02 ,  G11C29/12 ,  G11C29/14 ,  G11C29/16 ,  G11C29/36 ,  G11C29/38 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a device for testing a memory having a write cycle and read cycle. SOLUTION: A BIST state machine 60 and XOR circuit 68 change the data impressed upon the DI port of a memory to a value which is different from that of the data stored at a currently addressed memory position in a read cycle. In addition, the value of anticipated data generated by the BIST becomes different front that of the data on the DI port side of the memory, but the same as that of the data stored at the current memory address. When this constitution is used, such a flash through defect which could not be detected with the conventional BIST machine becomes detectable.