公开(公告)号：JPH08328964A

公开(公告)日：1996-12-13

申请号：JP12731896

申请日：1996-05-22

Applicant: IBM

Inventor： ADAMS ROBERT DEAN ,  CONNOR JOHN ,  KOCH GARRETT STEPHEN ,  TERNULLO LUIGI JR

IPC: G06F12/16 ,  G11C29/02 ,  G11C29/12 ,  G11C29/14 ,  G11C29/16 ,  G11C29/36 ,  G11C29/38 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a device for testing a memory having a write cycle and read cycle. SOLUTION: A BIST state machine 60 and XOR circuit 68 change the data impressed upon the DI port of a memory to a value which is different from that of the data stored at a currently addressed memory position in a read cycle. In addition, the value of anticipated data generated by the BIST becomes different front that of the data on the DI port side of the memory, but the same as that of the data stored at the current memory address. When this constitution is used, such a flash through defect which could not be detected with the conventional BIST machine becomes detectable.