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公开(公告)号：FR2311355A1
公开(公告)日：1976-12-10
申请号：FR7610913
申请日：1976-04-09
Applicant: IBM
Inventor： CROSS JON L , HOMAN MERLE E , MACHOL GUENTHER K , MALM RICHARD L , SVELUND LARRY E
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Patent Agency Ranking
公开(公告)号：DE2961563D1
公开(公告)日：1982-02-04
申请号：DE2961563
申请日：1979-11-19
Applicant: IBM
Inventor： MACHOL GUENTHER KEITH , CROSS JON L
IPC: H01L21/82 , H01L27/112 , H03K19/177 , H03K19/02 , H01L27/02 , H01L27/10
Abstract: A programmable logic array (PLA) comprising a search array in which the logical AND of one or more inputs (product terms) is formed and coupled to a read array in which each output is formed from a logical OR of one or more of the inputs from the search array. The array has a plurality of output circuits and each output circuit comprises a plurality of physical gates (one gate for each product term input), a common drain diffusion, a load device and an output connection. A plurality of output circuits is formed in each column of the read array and, where circuits overlap so that they cannot be placed in the same column, they are placed in adjacent columns. Where a plurality of outputs share a common product term, gates driven by the same product term are placed in adjacent columns, where they are connected by metal to the common product term ouptut from the search array. The ability to take outputs from the top, side or bottom of the array and to take a plurality of outputs from each column of the read array minimizes the area required for the array and produces performance improvements in array operation.
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公开(公告)号：CA1066812A
公开(公告)日：1979-11-20
申请号：CA252273
申请日：1976-05-11
Applicant: IBM
Inventor： CROSS JON L , HOMAN MERLE E , MACHOL GUENTHER K , MALM RICHARD L , SVELUND LARRY E
Abstract: APPARATUS FOR CONTROL AND DATA TRANSFER BETWEEN A SERIAL DATA TRANSMISSION MEDIUM AND A PLURALITY OF DEVICES Apparatus under microprocessor control for use in communicating over a serial communication loop with a remote attached control unit. It is capable of establishing frame synchronization, interpreting commands, assembling data and transmitting bits on the loop. The apparatus also communicates with I/O devices over a demand/response interface. A microprocessor interface with the loop includes loop sync control which establishes bit synchronization and generates a restart pulse at bit receive time and bit send time. The execution of instructions by the microprocessor is stopped and the microprocessor enters a wait state when it has finished all previous work and is ready to receive a loop bit. When it is time to receive the loop bit the microprocessor is restarted in response to the restart pulse from the loop synchronization. or output operations to a device, the microprocessor loads the device address and a device command or data into shift registers and initiates the transfer by setting a latch. When the transfer to the device is completed, this latch is reset in response to a signal from the device.
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