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公开(公告)号：FR2673015B1
公开(公告)日：1994-12-16
申请号：FR9011626
申请日：1990-09-20
Applicant: IBM
Inventor： MALM RICHARD LAVERNE , MEILEY CHARLES L
Abstract: An improved technique for processing large amounts of information and displaying that information graphically. The graphic display focuses attention to suspect areas employing colors and shading techniques to quickly focus the user's attention to problem areas. Multidimensional objects clearly convey global information concerning circuits employing millions of networks of electrical characteristics.
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公开(公告)号：GB2273804A
公开(公告)日：1994-06-29
申请号：GB9404022
申请日：1994-03-02
Applicant: IBM
Inventor： MALM RICHARD LAVERNE , MEILEY CHARLES L
Abstract: An improved technique for processing large amounts of information and displaying that information graphically. The graphic display focuses attention to suspect areas employing colours and shading techniques to quickly focus the users attention to problem areas. The display shows selected net states across respective raster lines e.g. N21, N20 etc for a selected period of a VLSI circuit simulation. As the net states changes between logic 1, logic zero or an undefined state, the colour of the raster line changes. The large number of nets which can thus be displayed and the time sequence of changing states can enable rapid evaluation of the VLSI circuit performance and the existence of errors or faults in the design.
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公开(公告)号：GB2268291A
公开(公告)日：1994-01-05
申请号：GB9015322
申请日：1990-07-12
Applicant: IBM
Inventor： MALM RICHARD LAVERNE , MEILEY CHARLES L
Abstract: An improved technique for processing large amounts of information and displaying that information graphically. The graphic display focuses attention to suspect areas employing colors and shading techniques to quickly focus the user's attention to problem areas. Multidimensional objects clearly convey global information concerning circuits employing millions of networks of electrical characteristics.
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公开(公告)号：DE3063100D1
公开(公告)日：1983-06-16
申请号：DE3063100
申请日：1980-06-24
Applicant: IBM
Inventor： COCKE JOHN , MALM RICHARD LAVERNE , SHEDLETSKY JOHN JAMES
Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
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公开(公告)号：AU1413776A
公开(公告)日：1977-12-01
申请号：AU1413776
申请日：1976-05-20
Applicant: IBM
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Patent Agency Ranking
公开(公告)号：DE2619462A1
公开(公告)日：1976-11-18
申请号：DE2619462
申请日：1976-05-03
Applicant: IBM
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公开(公告)号：GB2273804B
公开(公告)日：1994-11-16
申请号：GB9404022
申请日：1994-03-02
Applicant: IBM
Inventor： MALM RICHARD LAVERNE , MEILEY CHARLES L
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公开(公告)号：GB2268291B
公开(公告)日：1994-06-01
申请号：GB9015322
申请日：1990-07-12
Applicant: IBM
Inventor： MALM RICHARD LAVERNE , MEILEY CHARLES L
Abstract: An improved technique for processing large amounts of information and displaying that information graphically. The graphic display focuses attention to suspect areas employing colors and shading techniques to quickly focus the user's attention to problem areas. Multidimensional objects clearly convey global information concerning circuits employing millions of networks of electrical characteristics.
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公开(公告)号：IT1150956B
公开(公告)日：1986-12-17
申请号：IT2260580
申请日：1980-06-06
Applicant: IBM
Inventor： COCKE JOHN , MALM RICHARD LAVERNE , SHEDLETSKY JOHN JAMES
Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
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公开(公告)号：IT8022605D0
公开(公告)日：1980-06-06
申请号：IT2260580
申请日：1980-06-06
Applicant: IBM
Inventor： COCKE JOHN , MALM RICHARD LAVERNE , SHEDLETSKY JOHN JAMES
Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
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