公开(公告)号：JP2003016123A

公开(公告)日：2003-01-17

申请号：JP2002102222

申请日：2002-04-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CURRAN BRIAN W ,  LACEY LISA BRYANT ,  NORTHROP GREGORY A ,  PURI RUCHIR ,  STOK LEON

IPC: G06F17/50 ,  H01L21/82 ,  H03K19/096 ,  H03K19/20

CPC classification number: G06F17/505

Abstract: PROBLEM TO BE SOLVED: To provide a tapered gate and a synthesis method for improving the quality of synthesized circuit mounting.
SOLUTION: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce delay through some of input pins. For example in a tapered NAND gate, the bottom devices in a NFET stack are to have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies an input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of timing critical paths. The latest arriving gate input net is swapped with a net connected to the top pin. The gate is then converted to a tapered gate and is given paths going through the bottom gate input(s) that are not timing critical.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于提高合成电路安装质量的锥形栅极和合成方法。 解决方案：一个高性能门库增加了锥形门。 改变堆叠器件的宽度以减少一些输入引脚的延迟。 例如在锥形NAND门中，NFET堆叠中的底部器件将具有比顶部器件更长的宽度，以牺牲较大的底部输入到输出引脚延迟为代价，从而实现较小的顶部输入以输出引脚延迟。 使用合成算法的方法将输入网络修改为栅极引脚连接，并与具有锥形栅极的传统非锥形栅极交换，以改善时序关键路径的延迟。 最新的到达门输入网络与连接到顶部引脚的网络互换。 然后将栅极转换为锥形栅极，并给出通过不是时序关键的底栅输入的路径。

公开(公告)号：BR9103526A

公开(公告)日：1992-05-12

申请号：BR9103526

申请日：1991-08-16

Applicant: IBM

Inventor： CURRAN BRIAN W

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/401 ,  G06F12/00

Abstract: A programmable memory controller communicates starting word transfer information with fetch column addresses to assist memory support circuitry interfacing with page mode dynamic random access memory (DRAM) modules. This transfer information is normally provided to the memory support circuitry just before selection of the starting transfer data word from the fetch data line buffer. Memory latency can be reduced when transfer information is available to the support circuitry as it drives column addresses and/or column address strobe signals to the DRAMs.

公开(公告)号：GB2530782A

公开(公告)日：2016-04-06

申请号：GB201417446

申请日：2014-10-02

Applicant: IBM

Inventor： WEBEL TOBIAS ,  CURRAN BRIAN W ,  WARNOCK JAMES D ,  RIZZOLO RICHARD F ,  LOBO PREETHAM M

IPC: G06F1/28 ,  G06F9/50

Abstract: Disclosed is a processor with a common supply rail, and some processor cores that share the common supply rail. Each of the cores output a core dIPC value and receives as an input a core throttling signal. The processor has a chip power management logic 301 which has inputs 302 - 309 for the dIPC values, a threshold register 334 for a dIPC threshold value, chip dIPC register 319 to hold a current global dIPC value based on the average of the core values, and dIPC history registers 320 - 327 holding historic global values with an average historic global value stored in a register 331. There is a subtraction unit 332 to provide an absolute difference of an average historic global dIPC value based on the historic global dIPC value and the current dIPC values. A magnitude comparator 333 provides a throttling signal when the absolute difference is above the dIPC threshold value, which is output 310 - 317 to the processor cores.