公开(公告)号：EP1872402A4

公开(公告)日：2008-06-11

申请号：EP06758334

申请日：2006-04-13

Applicant: IBM

Inventor： WARNOCK JAMES D ,  SMITH GEORGE E III

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L27/088 ,  H01L29/7833 ,  H01L29/78615

Abstract: A first or primary field effect transistor ('FET') (620) is separated from a body contact thereto by one or more second FETs (632) that are placed electrically in parallel with the first FET (620). In this way, the body of the first FET (620) can be extended into the region occupied by the second FET (632) to allow contact to be made to the body of the first FET (620). In one embodiment, the gate conductor of the first FET (620) and a gate conductor of the second FET (632) are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.

公开(公告)号：JP2005080295A

公开(公告)日：2005-03-24

申请号：JP2004244947

申请日：2004-08-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WARNOCK JAMES D ,  WENDEL DIETER

IPC: H03K3/3562 ,  G06F1/06 ,  H03K3/037

CPC classification number: G06F1/06 ,  H03K3/0372

Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for operating master and slave latches. SOLUTION: In a first embodiment, a method for operating a master latch and a slave latch coupled to the master latch is provided. The method includes steps of attempting to operate the master latch and the slave latch in a first mode in which (1) the master latch is held in an open condition; and (2) the slave latch is pulsed so as to latch data passed through the open master latch. If the master latch and the slave latch do not operate in the first mode, the master latch and the slave latch are operated in a second mode in which (1) a first clock signal is employed to latch data with the master latch; and (2) a second clock signal is employed to latch data latched by the master latch with the slave latch. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于操作主从锁存器的方法和装置。 解决方案：在第一实施例中，提供了一种用于操作耦合到主锁存器的主锁存器和从锁存器的方法。 该方法包括以第一模式操作主锁存器和从锁存器的步骤，其中（1）主锁存器保持在打开状态; 和（2）从锁存器被脉冲以锁定通过打开的主锁存器的数据。 如果主锁存器和从锁存器不在第一模式下操作，则主锁存器和从锁存器在第二模式下操作，其中（1）使用第一时钟信号来与主锁存器锁存数据; 和（2）第二时钟信号用于锁存由主锁存器锁存的数据与从锁存器。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006113395A3

公开(公告)日：2007-03-08

申请号：PCT/US2006013987

申请日：2006-04-13

Applicant: IBM ,  WARNOCK JAMES D ,  SMITH GEORGE E III

Inventor： WARNOCK JAMES D ,  SMITH GEORGE E III

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L27/088 ,  H01L29/7833 ,  H01L29/78615

Abstract: A first or primary field effect transistor ("FET") (620) is separated from a body contact thereto by one or more second FETs (632) that are placed electrically in parallel with the first FET (620). In this way, the body of the first FET (620) can be extended into the region occupied by the second FET (632) to allow contact to be made to the body of the first FET (620). In one embodiment, the gate conductor of the first FET (620) and a gate conductor of the second FET (632) are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.

Abstract translation: 第一或主要场效应晶体管（“FET”）（620）通过与第一FET（620）并联放置的一个或多个第二FET（632）与其体接触分离。 以这种方式，第一FET（620）的主体可以延伸到由第二FET（632）占据的区域中，以允许与第一FET（620）的主体接触。 在一个实施例中，第一FET（620）的栅极导体和第二FET（632）的栅极导体是整体导电图案的整体部分。 整体式导电图案理想地小，并且可以制成与包括身体接触的FET的集成电路上的栅极导体的最小预定线宽一样小。 以这种方式，面积和寄生电容保持较小。

公开(公告)号：DE602006011595D1

公开(公告)日：2010-02-25

申请号：DE602006011595

申请日：2006-04-13

Applicant: IBM

Inventor： WARNOCK JAMES D ,  SMITH GEORGE E

IPC: H01L27/01

Abstract: A first or primary field effect transistor ("FET") is separated from a body contact thereto by one or more second FETs that are placed electrically in parallel with the first FET. In this way, the body of the first FET can be extended into the region occupied by the second FET to allow contact to be made to the body of the first FET. In one embodiment, the gate conductor of the first FET and a gate conductor of the second FET are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.

公开(公告)号：GB2530782A

公开(公告)日：2016-04-06

申请号：GB201417446

申请日：2014-10-02

Applicant: IBM

Inventor： WEBEL TOBIAS ,  CURRAN BRIAN W ,  WARNOCK JAMES D ,  RIZZOLO RICHARD F ,  LOBO PREETHAM M

IPC: G06F1/28 ,  G06F9/50

Abstract: Disclosed is a processor with a common supply rail, and some processor cores that share the common supply rail. Each of the cores output a core dIPC value and receives as an input a core throttling signal. The processor has a chip power management logic 301 which has inputs 302 - 309 for the dIPC values, a threshold register 334 for a dIPC threshold value, chip dIPC register 319 to hold a current global dIPC value based on the average of the core values, and dIPC history registers 320 - 327 holding historic global values with an average historic global value stored in a register 331. There is a subtraction unit 332 to provide an absolute difference of an average historic global dIPC value based on the historic global dIPC value and the current dIPC values. A magnitude comparator 333 provides a throttling signal when the absolute difference is above the dIPC threshold value, which is output 310 - 317 to the processor cores.