公开(公告)号：JP2006221622A

公开(公告)日：2006-08-24

申请号：JP2006016958

申请日：2006-01-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FLEISCHER BRUCE M ,  HAESS JUERGEN ,  KROENER MICHAEL ,  MARTIN S SHUMUUKURAA ,  SCHWARZ ERIC M ,  DAO-TRONG SON

IPC: G06F7/76

CPC classification number: G06F7/483 ,  G06F7/499 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/5443 ,  G06F2207/382

Abstract: PROBLEM TO BE SOLVED: To improve performance of a floating point unit which performs feedback prior to normalization or rounding. SOLUTION: This system is for performing floating point arithmetic operation including an input register adapted for receiving an operand. This system further includes a mechanism for performing shifting or masking operation in response to determination that the operand is a un-normalization format. The system further includes an instruction for performing single-precision increment of the operand in response to determination that the operand is single-precision, that the operand requires the incrementing based on the result of previous operation and that the previous operation has not performed the incrementing. The operand is created in the previous operation. The system further includes an instruction for performing double precision incrementing of the operand in response to determination that the operand is double precision, that the operand requires the incrementing based on the result of the previous operation and that the previous operation has not performed the incrementing. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提高在归一化或舍入之前执行反馈的浮点单元的性能。

解决方案：该系统用于执行浮点运算，包括适于接收操作数的输入寄存器。 该系统还包括用于响应于操作数是非归一化格式的确定而执行移位或掩蔽操作的机制。 该系统还包括响应于确定操作数是单精度来执行操作数的单精度增量的指令，操作数基于先前操作的结果需要增加，并且先前的操作没有执行递增 。 操作数是在上一操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：CA2006228C

公开(公告)日：1994-10-25

申请号：CA2006228

申请日：1989-12-20

Applicant: IBM

Inventor： DAO-TRONG SON ,  GETZLAFF KLAUS J ,  HELWIG KLAUS

IPC: G06F7/533 ,  G06F7/52 ,  G06F7/53 ,  G06F9/302

Abstract: A multiplier for multiplying two binary operands comprising an encoding unit, a multiplying unit composed of two multiplying arrays and a logic unit. The encoding unit to which a second operand is supplied generates factors following the Booth algorithm. The two multiplying arrays are respectively supplied with a first operand and factors belonging to the higher significance digits, respectively, of the second operand. Both multiplying arrays simultaneously multiply the factors with the first operand into respective partial end products. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.

公开(公告)号：BR9000776A

公开(公告)日：1991-01-22

申请号：BR9000776

申请日：1990-02-20

Applicant: IBM

Inventor： DAO-TRONG SON ,  GETZLAFF KLAUS JOERG ,  HELWIG KLAUS

IPC: G06F7/533 ,  G06F7/52 ,  G06F7/53