公开(公告)号：DE3072139D1

公开(公告)日：1989-02-02

申请号：DE3072139

申请日：1980-08-12

Applicant: IBM

Inventor： BAZLEN DIETER DR ,  BOCK DIETRICH ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  PAINKE HELMUT

IPC: G06F9/48 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46

Abstract: In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead. An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated. If the control signals need be grouped for physical reasons, it is possible to determine which of these signals are a function of forced operations. This will negate the need to otherwise distribute these control signals throughout the decoder, thereby reducing and simplifying the wiring required.

公开(公告)号：DE19848742C2

公开(公告)日：2002-05-02

申请号：DE19848742

申请日：1998-10-22

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/28

Abstract: A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.

公开(公告)号：BR8404462A

公开(公告)日：1985-09-03

申请号：BR8404462

申请日：1984-09-05

Applicant: IBM

Inventor： CHILINSKI HERBERT ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  RICHTER STEPHAN

IPC: G06F9/38 ,  G06F11/14 ,  G06F9/46

Abstract: In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.

公开(公告)号：DE19929051C2

公开(公告)日：2001-10-04

申请号：DE19929051

申请日：1999-06-25

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  LAUB OLIVER ,  PFEFFER ERWIN

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/38 ,  G06F9/32 ,  G06F9/318

Abstract: A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

公开(公告)号：CA2006228C

公开(公告)日：1994-10-25

申请号：CA2006228

申请日：1989-12-20

Applicant: IBM

Inventor： DAO-TRONG SON ,  GETZLAFF KLAUS J ,  HELWIG KLAUS

IPC: G06F7/533 ,  G06F7/52 ,  G06F7/53 ,  G06F9/302

Abstract: A multiplier for multiplying two binary operands comprising an encoding unit, a multiplying unit composed of two multiplying arrays and a logic unit. The encoding unit to which a second operand is supplied generates factors following the Booth algorithm. The two multiplying arrays are respectively supplied with a first operand and factors belonging to the higher significance digits, respectively, of the second operand. Both multiplying arrays simultaneously multiply the factors with the first operand into respective partial end products. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.

公开(公告)号：DE19929051A1

公开(公告)日：2000-02-24

申请号：DE19929051

申请日：1999-06-25

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  LAUB OLIVER ,  PFEFFER ERWIN

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/38

Abstract: The data processing system is designed to handle a mixed sequence of 64 and 32 bit long instructions by using an identification process based around the register contents. The 32 bit instruction is located and is copied into a target register . The copy source and register numbers are listed in table form.

公开(公告)号：DE19848742A1

公开(公告)日：1999-06-24

申请号：DE19848742

申请日：1998-10-22

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/28

Abstract: The system includes an arrangement of physical storage registers which form instances of logical registers. A sequence list associates each logical register with a corresponding physical register, and a connection list associates a physical register which forms an instance of a logical register, to a physical register of an earlier, preceding instance of the same logical register, to form a chain of physical registers according to a sequence of instructions. An Independent claim is provided for a method associating physical registers with logical registers.

公开(公告)号：CA1191615A

公开(公告)日：1985-08-06

申请号：CA429597

申请日：1983-06-03

Applicant: IBM

Inventor： CHILINSKI HERBERT ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  RAETH FRANZ J

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318

Abstract: ARRANGEMENT IN THE INSTRUCTION UNIT OF A MICROPROGRAM-CONTROLLED PROCESSOR FOR THE DIRECT HARDWARE-CONTROLLED EXECUTION OF PARTICULAR INSTRUCTIONS In a microprogram-controlled processor, having an additional operating mode in which particular functions can be executed under direct hardware control, a mode latch is provided signalizing the instruction decoder whether micro program instructions or directly controlled macro instructions are to be executed. The microprogram instructions are executed in the usual manner. For the execution of the directly controlled macro instructions, the control storage of the processor is not required for supplying micro instructions. Instead, this storage with the operation decoder as an address supplies one or several hardware control words. The hardware control words consist of individual control bits, each of which directly controls one hardware function.