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    METHOD AND SYSTEM FOR ISSUING INSTRUCTION
    1.
    发明专利
    METHOD AND SYSTEM FOR ISSUING INSTRUCTION 失效

    公开(公告)号：JPH10283178A

    公开(公告)日：1998-10-23

    申请号：JP4930398

    申请日：1998-03-02

    Applicant: IBM

    Inventor： GETZLAFF KLAUS JOERG ,  LEPPLA BERND ,  PFEFFER ERWIN ,  PFLUEGER THOMAS ,  WITHELM BIRGIT

    IPC: G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To issue an instruction to an execution unit even at the time of a continuous sequence and back-to-back in a random processing system by setting the valid bit of the target operand before the target operand of the instruction becomes usable. SOLUTION: The instruction is taken out from an instruction memory 100 and successively buffered in an instruction cache 101, then the instruction is decoded to a common internal instruction format and then, the instruction is transferred to a reservation station 103. In the reservation station 103, the instruction stands by until issuance to one of function units can be performed. In such a random processing system, the valid bit of the target operand is set before the target operand of the instruction becomes usable. A source operand is generated as the target operand of a preceding instruction and the instruction is immediately issued when the valid bit is set to the entire source operands.

    Compressed data expansion method
    3.
    发明专利
    Compressed data expansion method 未知

    公开(公告)号：DE4342521C1

    公开(公告)日：1995-07-13

    申请号：DE4342521

    申请日：1993-12-14

    Applicant: IBM

    Inventor： KOEHLER THOMAS ,  GETZLAFF KLAUS JOERG ,  KOESTER RALPH ,  STOEHR TILMANN ,  KOHLER HELMUT ,  SCHUMACHER NORBERT

    IPC: H03M7/30 ,  G06F17/00

    Abstract: The method uses source and target registers (15,16,26 to 29) to alternately receive and take out data blocks of predefined lengths. Index symbols are selected from the contacts of the source register and used as addresses of dictionary memory (14) whose entries contain expanded data in the form of variable length character symbols. Data blocks of predefined lengths are formed from the character symbols and stored in target registers. A divider (22), a multiplexer circuit and control circuit dynamically select the target register to alternately load the target register and transmit complete data blocks to memory.

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