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    Method and device for reducing sidewall conduction in recessed oxide pet arrays
    7.
    发明授权
    Method and device for reducing sidewall conduction in recessed oxide pet arrays 失效
    用于减少凹陷氧化物宠物阵列中的侧壁导电的方法和装置

    公开(公告)号：US3899363A

    公开(公告)日：1975-08-12

    申请号：US48403374

    申请日：1974-06-28

    Applicant: IBM

    Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L ,  WALKER EDWARD J

    IPC: H01L27/088 ,  H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L27/08

    CPC classification number: H01L21/76216 ,  H01L21/00 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/7621 ,  Y10S148/051

    Abstract: Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistors (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide therein. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.

    Abstract translation: 使用硅半导体场效应晶体管（FET）制造用于高速存储器和逻辑应用的紧密集成的集成电路阵列，其通过完全凹陷的氧化物隔离区彼此电隔离。 制造方法的特征在于将凹陷氧化物的侧壁的有害源降低到漏极导通的程度比FET的主沟道的电流更小。 离子注入用于在邻近侧壁区域和凹陷氧化物下面的硅衬底中提供额外的掺杂浓度。 凹陷氧化物下面的多余掺杂剂用作寄生通道阻挡层。 在其中形成凹陷的氧化物之前，通过将硅衬底中的倾斜侧壁植入，来促进侧壁掺杂。 倾斜的侧壁通过利用与<100>取向的p导电型基底组合的各向异性蚀刻来实现。

    Insulated gate field effect transistor memory array
    8.
    发明授权
    Insulated gate field effect transistor memory array 失效
    绝缘栅场效应晶体管存储器阵列

    公开(公告)号：US3609712A

    公开(公告)日：1971-09-28

    申请号：US3609712D

    申请日：1969-01-15

    Applicant: IBM

    Inventor： DENNARD ROBERT H

    IPC: G11C11/41 ,  G11C7/02 ,  G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  G11C11/40 ,  H03K3/286

    CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419

    Abstract: A bit oriented integrated circuit insulated gate field effect transistor memory array is disclosed which includes decoding on a semiconductor chip for both word and bit lines. Decoders which incorporate a combination of NOR logic elements and inverters provide for selection of a pair of bit lines and a single word line such that information can be written into a field effect transistor bistable circuit memory cell associated with these word and bit lines. Decoder controlled bit line switches in the form of field effect transistors are enabled to close the circuit between the bit driver and a column of memory cells. Also disclosed is a bit line biasing technique which eliminates the possibility of false writing into unselected memory cells. This is accomplished by applying a voltage via a resistance to the bit lines or by intermittently applying an appropriate voltage to the bit conductors associated with unselected memory cells.

    Memory cell using gate control diode and its usage, semiconductor structure
    10.
    发明专利
    Memory cell using gate control diode and its usage, semiconductor structure 有权
    使用门控二极管的存储单元及其使用，半导体结构

    公开(公告)号：JP2006190363A

    公开(公告)日：2006-07-20

    申请号：JP2005000192

    申请日：2005-01-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LUK WING K ,  DENNARD ROBERT H

    IPC: G11C11/405 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide an advanced 3T1D memory cell having a readout selection switch and a readout switch. SOLUTION: The memory cell has (1) a writing switch 1325 for which a 1st terminal is coupled with a bit line and a control terminal is combined with a 1st control line, (2) a 2-terminal semiconductor device 1330 for which a 1st terminal of the 2-terminal semiconductor device is coupled with the 2nd terminal of the writing switch, a 2nd terminal is coupled with at least one of a 2nd control line, and the capacitance when the voltage of the 1st terminal against the 2nd terminal is exceeding the threshold voltage becomes larger than the capacitance not exceeding the threshold voltage, (3) a readout selection switch 1340 for which the control terminal is coupled with the 2nd control line, and the 1st terminal is coupled with the bit line, and (4) a readout switch 1345 for which the control terminal is coupled with a 1st terminal of the gate control diode and the 2nd terminal of the writing switch, the 1st terminal is coupled with the 2nd terminal of the readout selection gate, and further the 2nd terminal is grounded. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有读出选择开关和读出开关的高级3T1D存储单元。 解决方案：存储单元具有：（1）写入开关1325，第一端子与位线耦合，控制端子与第一控制线路组合;（2）2端子半导体器件1330，用于 其中2端子半导体器件的第一端子与写入开关的第二端子耦合，第二端子与第二控制线路中的至少一个耦合，并且当第一端子对于第二端子的电压为第二端子时的电容 端子超过阈值电压变得大于不超过阈值电容的电容，（3）控制端与第二控制线耦合的读出选择开关1340，第一端与位线耦合， （4）读出开关1345，控制端与门控制二极管的第一端和写开关的第二端耦合，第一端与读出选择栅的第二端耦合， r第二个端子接地。 版权所有（C）2006，JPO＆NCIPI

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