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    NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS
    1.
    发明公开
    NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS 审中-公开
    相变材料内容可寻址存储器元件不挥发存储器

    公开(公告)号：EP1908076A4

    公开(公告)日：2009-06-17

    申请号：EP06737703

    申请日：2006-03-09

    Applicant: IBM

    Inventor： HSU LOUIS L C ,  JI BRIAN L ,  LAM CHUNG HON ,  WONG HON-SUM PHILIP

    IPC: G11C11/24

    CPC classification number: G11C13/0004 ,  G11C15/046

    Abstract: A non- volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read- write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit- read-write-search-line, and a drain connected to another end of the second phase change material element.

    Associative memory array
    4.
    发明专利
    Associative memory array 有权
    相关记忆阵列

    公开(公告)号：JP2011048894A

    公开(公告)日：2011-03-10

    申请号：JP2010180536

    申请日：2010-08-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MONTOYE ROBERT KEVIN ,  DITLOW GARY ,  JI BRIAN L ,  CHANG LELAND

    IPC: G11C15/04 ,  G11C13/00

    CPC classification number: G11C15/046 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004

    Abstract: PROBLEM TO BE SOLVED: To provide a memory device used particularly for an associative memory, a method for operating the associative memory, and a system including the associative memory. SOLUTION: The memory device for storing one or a plurality of addresses includes a coincidence line and first and second memory cells forming a two-bit memory cell. Each memory cell includes two memory elements connected to the coincidence line, and a selection line connected there. The selection line provides a signal expression of logical combinations of at least two different inputs. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供特别用于关联存储器的存储器件，用于操作关联存储器的方法以及包括关联存储器的系统。 解决方案：用于存储一个或多个地址的存储器件包括一致线和形成两位存储器单元的第一和第二存储器单元。 每个存储单元包括连接到重合线的两个存储元件，以及连接在该存储单元上的选择线。 选择线提供至少两个不同输入的逻辑组合的信号表达。 版权所有（C）2011，JPO＆INPIT

    RANDOM ACCESS MEMORY USING BLOCK ADDRESS
    5.
    发明专利
    RANDOM ACCESS MEMORY USING BLOCK ADDRESS 失效

    公开(公告)号：JPH11317073A

    公开(公告)日：1999-11-16

    申请号：JP1817499

    申请日：1999-01-27

    Applicant: IBM

    Inventor： JI BRIAN L ,  KIRIHATA TOSHIAKI

    IPC: G11C11/407 ,  G11C8/10 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To provide a random access memory in which current scattering, voltage drops and heat generation related to the access of blocks in first and second storage units of a double memory unit are stabilized. SOLUTION: The memory is arranged between first and second storage units 220 and 222 and include a row selection unit 224 which conducts accesses to the storage places of the units 220 and 222 in accordance with first and second selection signals that are transmitted from the external side end section of the double memory unit to the selected row places. Different numbers are assigned to the blocks located at the distances corresponding from the external side end section so that the sum of the lengths of the propagation of the first and the second selection signals to the numbered blocks is maintained in a relatively constant manner regardless of the block number selected for the access.

    Common row decoder
    7.
    发明专利
    Common row decoder 有权
    通用解码器

    公开(公告)号：JPH11273344A

    公开(公告)日：1999-10-08

    申请号：JP1816399

    申请日：1999-01-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： JI BRIAN L ,  KIRIHATA TOSHIAKI

    IPC: G11C11/407 ,  G11C8/10 ,  G11C11/401 ,  G11C11/409

    CPC classification number: G11C8/10

    Abstract: PROBLEM TO BE SOLVED: To obtain a common row decoder and a common row decoding method for supplying selection signals independently timing-controlled of each other to a first memory unit and a second memory unit, respectively.
    SOLUTION: A common row decoder 110 includes an address input circuit 111 for supplying an enable input or a disable input in response to conditions of address signals XPs. Furthermore, a first and second selection circuits are provided for supplying selection signals RDOUT independently timing-controlled of each other to the first and second memory units, respectively, in response to first and second block selection inputs BLKSEL, enable conditions of first and second timing signals RDECON, and the enable input of the address input circuit.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：为了获得共同的行解码器和公共行解码方法，分别将第一存储单元和第二存储单元独立地进行定时控制的选择信号。 解决方案：公共行解码器110包括地址输入电路111，用于响应于地址信号XPs的条件提供使能输入或禁止输入。 此外，提供第一和第二选择电路，用于响应于第一和第二块选择输入BLKSEL，分别为第一和第二存储器单元提供彼此独立地定时控制的选择信号RDOUT，使第一和第二定时的使能条件 信号RDECON和地址输入电路的使能输入。

    MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME
    8.
    发明申请
    MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME 审中-公开
    多发生器，部分阵列Vt，跟踪系统，以提高阵列保持时间

    公开(公告)号：WO0193271A2

    公开(公告)日：2001-12-06

    申请号：PCT/US0117267

    申请日：2001-05-25

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU LOUIS L ,  WEINFURTNER OLIVER ,  JI BRIAN L

    IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

    CPC classification number: G11C8/08 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4078 ,  G11C2207/104

    Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

    Abstract translation: 通过使用以一小部分监视晶体管阈值电压跟踪的偏置电压调节来获得改进的晶体管阵列器件性能。 电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。 这些优点是特别是当通过至少一个监视晶体管的实际阈值电压的一部分进行跟踪来调节通常提供给阵列的至少两个偏置电压时。 性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗以及（在存储器单元的情况下）改进的保留时间。

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