公开(公告)号：MY124875A

公开(公告)日：2006-07-31

申请号：MYPI20010539

申请日：2001-02-07

Applicant: IBM

Inventor： SESHADRI SUBBANNA ,  DOUGLAS DUANE COOLBAUGH ,  GREGORY G FREEMAN

IPC: H01L21/331 ,  H01L31/119 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/108 ,  H01L29/73 ,  H01L29/737 ,  H01L29/76 ,  H01L29/94

Abstract: A METHOD OF FORMING A POLY-POLY CAPACITOR (49), A MOS TRANSISTOR (18), AND A BIPOLAR TRANSISTOR (48) SIMULTANEOUSLY ON A SUBSTRATE (10) COMPRISING THE STEPS OF THE DEPOSITING AND PATTERNING A FIRST LAYER (26) OF POLYSILICON ON THE SUBSTRATE TO FORM A FIRST PLATE ELECTRODE CAPASITOR AND ON AN ELECTRODE OF THE MOS TRANSISTOR, AND DEPOSISTING AND PATTERINING A SECOND LAYER (42) OF POLYSILICON ON THE SUBTRATE TO FORM A SECOND PLATE ELECTRODE OF SAID CAPACITOR AND AN ELECTRODE OF THE BIPOLAR TRANSISTOR.(FIG. 1F)

公开(公告)号：SG108241A1

公开(公告)日：2005-01-28

申请号：SG200101030

申请日：2001-02-22

Applicant: IBM

Inventor： DOUGLAS DUANE COOLBAUGH ,  GREGORY GOWER FREEMAN ,  SESHADRI SUBBANNA

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/737 ,  H01L27/08

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.

公开(公告)号：SG107561A1

公开(公告)日：2004-12-29

申请号：SG200101931

申请日：2001-03-26

Applicant: IBM

Inventor： DOUGLAS DUANE COOLBAUGH ,  JAMES STUART DUNN ,  STEPHEN ARTHUR ST ONGE

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/94

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

公开(公告)号：SG96266A1

公开(公告)日：2003-05-23

申请号：SG200107801

申请日：2001-12-13

Applicant: IBM

Inventor： DOUGLAS DUANE COOLBAUGH ,  JAMES STUART DUNN ,  STEPHEN ARTHUR ST ONGE

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/8228

Abstract: A method is provided for fabricating a poly-poly capacitor integrated with a BiCMOS process. This includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor. An upper SiGe plate electrode is then formed during growth of a SiGe base region of a heterojunction bipolar transistor.