公开(公告)号：JP2005026689A

公开(公告)日：2005-01-27

申请号：JP2004192192

申请日：2004-06-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GREGORY G FREEMAN ,  KHATER MARWAN H ,  PAGETTE FRANCOIS

IPC: H01L29/737 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/10 ,  H01L29/732

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To provide a self-adjusting bipolar transistor structure having a projecting exogenous base provided with external and internal regions with different dope densities, and to provide its manufacturing method.
SOLUTION: The first material of a first dope density is provided so that an exogenous base external region is formed. Then, a first opening is formed in the first material's layer by lithography into which a dummy emitter pedestal is formed, and by which a trench is formed between a side wall of the first opening and the dummy pedestal. Thereafter, the second material of a second dope density is provided within this trench, and another exogenous base internal extension region is formed whose projecting external base marginal part self-adjusts to a dummy pedestal marginal part. Since the emitter is formed where there were the dummy pedestals, this exogenous base also self-adjusts to the emitter.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有突出的外源基底的自调节双极晶体管结构，其具有不同的浓度密度的外部和内部区域，并提供其制造方法。 解决方案：提供第一浓度密度的第一种材料，以便形成外源基底外部区域。 然后，通过光刻法在第一材料层中形成第一开口，在其中形成有虚拟发射极基座，并且在第一开口的侧壁和虚拟基座之间形成有沟槽。 此后，在该沟槽内设置第二掺杂浓度的第二材料，并且形成另外的外源基底内部延伸区域，其突出的外部基部边缘部分自调整到虚拟基座边缘部分。 由于发射器形成在具有虚拟基座的位置，所以这种外部基极也自发地调节到发射极。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004319983A

公开(公告)日：2004-11-11

申请号：JP2004085745

申请日：2004-03-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SUBBANNA SESHADRI ,  JAGANNATHAN BASANTH ,  GREGORY G FREEMAN ,  AHLGREN DAVID C ,  ANGELL DAVID ,  SCHONENBERG KATHRYN T ,  STEIN KENNETH J ,  JAMIN FEN F

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L27/0623

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS integrated circuit having a raised external base.
SOLUTION: This method comprises a step for forming a polycrystal silicon layer on the surface of a gate dielectric substance 18 provided on a substrate having a device section 14 in which a bipolar transistor is formed and a device section 16 in which a CMOS transistor is formed. Then, the polycrystal silicon layer is patterned, and a sacrifice polycrystal silicon layer is formed above the device section in which the bipolar transistor is formed and the section around it. Meanwhile, a gate conductor is provided in the device section in which the CMOS transistor is formed at the same time. Then, a spacer 30 is provided around each of the gate conductor. Then a part of the sacrifice polycrystal silicon layer on the bipolar device section is selectively removed to provide an opening in the device section in which the bipolar transistor is formed. Then the bipolar transistor having a raised external base 58 is formed at the opening.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成具有凸起的外部基底的BiCMOS集成电路的方法。 解决方案：该方法包括在设置在其上形成有双极晶体管的器件部分14的衬底上的栅极电介质18的表面上形成多晶硅层的步骤，以及器件部分16，其中CMOS 形成晶体管。 然后，对多晶硅层进行构图，在形成双极型晶体管的器件部分上方形成牺牲多晶硅层，并在其周围形成截面。 同时，在同时形成CMOS晶体管的器件部分中提供栅极导体。 然后，围绕每个栅极导体设置间隔件30。 然后，选择性地去除双极器件部分上牺牲多晶硅层的一部分，以在其中形成双极晶体管的器件部分中提供开口。 然后在开口处形成具有升高的外部基座58的双极晶体管。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004221582A

公开(公告)日：2004-08-05

申请号：JP2004003465

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SCHONENBERG KATHRYN T ,  GREGORY G FREEMAN ,  STRICKER ANDREAS D ,  RIEH JAE-SUNG

IPC: H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligning oxide mask formed by utilizing the difference in oxidation speed between different materials.
SOLUTION: The self-aligning oxide mask is formed on a CVD growth base NPN base layer including a single crystal Si52 (Si/SiGe) in an active area and a poly-crystal Si51 (Si/SiGe). The self-aligning mask is fabricated by utilizing the fact that the poly-crystal Si (Si/SiGe) oxidizes faster than the single crystal Si (Si/SiGe). By using the thermal oxidation method, a thick oxide layer is formed on the poly-crystal Si (Si/SiGe) and a thin oxide layer is formed on the single crystal Si (Si/SiGe), thereby the oxide films are formed on both the poly-crystal Si (Si/SiGe) and the single crystal Si (Si/SiGe), and by the control of etching of the oxide, the thin oxide layer on the single crystal Si (Si/SiGe) is removed while the self-alignment oxide mask layer is left on the poly-crystal Si (Si/SiGe).
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002329725A

公开(公告)日：2002-11-15

申请号：JP2002104250

申请日：2002-04-05

Applicant: IBM

Inventor： GREGORY G FREEMAN ,  GREENBERG DAVID R ,  JENG SHWU-JEN

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method to form a high performance hetero-junction bipolar transistor. SOLUTION: The invention includes a process to form two pairs of spacers at both ends of an emitter pedestal. After a first pair of spacers 130 is formed, a first outer base region 100 is formed at both ends of an intrinsic base. A second pair of spacers 160 is formed above the first pair of spacers 130. Then, a second outer base region 140 is formed at both ends of the intrinsic base. Two pairs of spacers enable the first outer base and the second outer base to have different widths. This brings about a structure of complex outer base that is adjacent to an emitter 22 and not adjacent to a collector 20 and consequently a base parasitic resistance reduces with the reduction of parasitic capacitance between the collector and outer base.

公开(公告)号：JP2002033395A

公开(公告)日：2002-01-31

申请号：JP2001160150

申请日：2001-05-29

Applicant: IBM

Inventor： GREGORY G FREEMAN ,  ROBERT A GROVES ,  JEFFREY JOHNSON ,  SESHADORI SUBANA ,  VOLANT RICHARD P

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082

Abstract: PROBLEM TO BE SOLVED: To improve the high-frequency performance of transistor design, and a manufacturing yield by combining processes from various techniques for eliminating and reducing the source of parasitic capacity. SOLUTION: Collector, base, and emitter regions are formed on a substrate, a second substrate is mounted, an original substrate is completely or partially removed, a non-active collector region is removed or is set to a semi-insulator, and wiring and contact are performed from the original back surface of a chip. A dielectric material used in a manufacturing process is removed, thus further reducing electrostatic capacity. A high-frequency transistor is jointed to a CMOS chip or a wafer, thus forming a BICMOS chip.

公开(公告)号：JP2006074040A

公开(公告)日：2006-03-16

申请号：JP2005247839

申请日：2005-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  GREGORY G FREEMAN ,  KHATER MARWAN H

IPC: H01L21/331 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/242 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a high-performance bipolar device and its manufacturing method.
SOLUTION: The method to increase electronic charge carrier mobility in a bipolar device includes the steps of generating compression strain in the device to increase hole mobility on the device's internal base, and causing tensile strain in the device to increase electron mobility on the internal base of the device. The compression strain and tensile strain are generated by forming a stress layer in the neighborhood of the internal base of the device. As for the stress layer, at least part of it is adjacent to an emitter structure of the device, and is imbedded in the device's base layer. The stress layer has a grating constant different from the internal base.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种高性能双极器件及其制造方法。 解决方案：在双极器件中增加电子载流子迁移率的方法包括以下步骤：在器件中产生压缩应变以增加器件内部基极上的空穴迁移率，并引起器件中的拉伸应变以增加电子迁移率 设备的内部基座。 压缩应变和拉伸应变通过在器件的内部基部附近形成应力层来产生。 至于应力层，其至少一部分与器件的发射极结构相邻，并嵌入器件的基极层。 应力层具有不同于内部基底的光栅常数。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005167203A

公开(公告)日：2005-06-23

申请号：JP2004291416

申请日：2004-10-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AHLGREN DAVID C ,  GREGORY G FREEMAN ,  KHATER MARWAN H ,  VOLANT RICHARD P

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor having self-aligned raised extrinsic base silicide and emitter contact border.
SOLUTION: The bipolar transistor exhibits the parasitic property which is more reduced than the parasitic property exhibited by a bipolar transistor which is not equipped with self-aligned silicide and a self-aligned emitter contact border. In a method of manufacturing the bipolar transistor structure, a block emitter polysilicon region is replaced with a conventional T-shaped emitter polysilicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有自对准凸起的外在基极硅化物和发射极接触边界的双极晶体管。 解决方案：双极晶体管表现出比由不配置自对准硅化物和自对准发射极接触边界的双极晶体管表现出的寄生特性降低的寄生特性。 在制造双极晶体管结构的方法中，块状发射极多晶硅区域被传统的T形发射极多晶硅替代。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004304190A

公开(公告)日：2004-10-28

申请号：JP2004090598

申请日：2004-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHATER MARWAN H ,  RIEH JAE-SUNG ,  STRICKER ANDREAS D ,  GREGORY G FREEMAN ,  SCHONENBERG KATHRYN T

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a bipolar transistor structure, capable of reducing the parasitic capacitance.
SOLUTION: A method for forming a vertical bipolar transistor, comprising the steps of forming a bipolar transistor on silicon semiconductor substrate 11 which has an upper surface; forming STI regions 14 which are made of dielectric materials and have an inside edge portion and an upper surface, respectively; forming a doped collector region C between a pair of STI regions; also forming a counter doped intrinsic base region IB between the pair of STI regions, wherein there is each margin between the intrinsic base region and the pair of STI regions, and the intrinsic base region has edges; forming a doped-emitter region on the intrinsic base region apart from the edges; and forming shallow separated extension regions IE made of dielectric materials in the above margins, and placing them in parallel with the edges of the intrinsic base region; and forming an outer base region which covers the shallow separated extension regions partially, and further extends to the intrinsic base region, thereby physically and electrically contacting with the intrinsic base region.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：MY134208A

公开(公告)日：2007-11-30

申请号：MYPI20021771

申请日：2002-05-16

Applicant: IBM

Inventor： GREGORY G FREEMAN ,  DAVID C AHLGREN ,  FENG YI HUANG ,  ADAM D TICKNOR

IPC: H01L29/76 ,  H01L21/00 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

Abstract: A PROCESS FOR FORMING A BIPOLAR TRANSISTOR WITH A RAISED EXTRINSIC BASE, AN EMITTER, AND A COLLECTOR INTEGRATER WITH A CMOS CIRCUIT WITH A GATE. AN INTERMEDIATE SEMICONDUCTOR STRUCTURE IS PROVIDED HAVING CMOS AND BIPOLAR AREAS. AN INTRINSIC BASE LAYER IS PROVIDED IN THE BIPOLAR AREA. A BASE OXIDE IS FORMED ACROSS, AND A SACRIFICIAL EMITTER STACK SILICON LAYER IS DEPOSITED ON, BOTH THE CMOS AND BIPOLAR AREAS. A PHOTORESISTIS APPLIED TO PROTECT THE BIPOLAR AREA AND THE STRUCTURE IS ETCHED TO REMOVE THE SACRIFICIAL LAYER FROM THE CMOS AREA ONLY SUCH THAT THE TOP SURFACE OF THE SACRIFICIAL LAYER ON THE BIPOLAR STOP LAYER IS DEPOSITED HAVING A SUBSTANTIALLY FLUSH WITH THE TOP SURFACE OF THE CMOS AREA. FINALLY, A POLISH STOP LAYER IS DEPOSITED HAVING A SUBSTANTIALLY FLAT TOP SURFACE ACROSS BOTHTHE CMOS AND BIPOLAR AREAS SUITABLE FOR SUBSEQUENT CHEMICAL-MECHANICAL POLISHING (CMP) TO FORM THE RAISED EXTRINSIC BASE.

公开(公告)号：MY124875A

公开(公告)日：2006-07-31

申请号：MYPI20010539

申请日：2001-02-07

Applicant: IBM

Inventor： SESHADRI SUBBANNA ,  DOUGLAS DUANE COOLBAUGH ,  GREGORY G FREEMAN

IPC: H01L21/331 ,  H01L31/119 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/108 ,  H01L29/73 ,  H01L29/737 ,  H01L29/76 ,  H01L29/94

Abstract: A METHOD OF FORMING A POLY-POLY CAPACITOR (49), A MOS TRANSISTOR (18), AND A BIPOLAR TRANSISTOR (48) SIMULTANEOUSLY ON A SUBSTRATE (10) COMPRISING THE STEPS OF THE DEPOSITING AND PATTERNING A FIRST LAYER (26) OF POLYSILICON ON THE SUBSTRATE TO FORM A FIRST PLATE ELECTRODE CAPASITOR AND ON AN ELECTRODE OF THE MOS TRANSISTOR, AND DEPOSISTING AND PATTERINING A SECOND LAYER (42) OF POLYSILICON ON THE SUBTRATE TO FORM A SECOND PLATE ELECTRODE OF SAID CAPACITOR AND AN ELECTRODE OF THE BIPOLAR TRANSISTOR.(FIG. 1F)