公开(公告)号：DE69016094D1

公开(公告)日：1995-03-02

申请号：DE69016094

申请日：1990-04-23

Applicant: IBM

Inventor： EBBERS TIMOTHY JON ,  GUPTA SATISH ,  HENDERSON RANDALL LAWRENCE ,  HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM ,  WILLIAMS TODD

IPC: G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C7/00 ,  G11C11/409

Abstract: In a video random access memory which includes an implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out, a control signal is provided which causes the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers, resulting in an ability to select a stopping point when scanning out of the serial access memory, thereby allowing both the starting and ending points of the data to be scanned out of the serial access memory, to be specified.

公开(公告)号：DE69030295D1

公开(公告)日：1997-04-30

申请号：DE69030295

申请日：1990-10-17

Applicant: IBM

Inventor： EBBERS TIMOTHY JON

IPC: G06T1/00 ,  G06T11/00 ,  G06T17/00

Abstract: Video random access memory having a random array and serial buffer is employed to speed the replication of structure state information used in the processing of hierarchical graphic data structures. Specialized circuitry in the video RAM and associated VRAM sequencer are used to perform a rapid transfer of structure state information from one row of the VRAM (the parent row) to a second VRAM row (the child row). The sequencer is modified to perform back to back read data transfer and write data transfer operation in response to a single graphics processor command. The return to previous structure state can be accomplished by readdressing the VRAM row containing the previous structure state.

公开(公告)号：DE69016094T2

公开(公告)日：1995-06-29

申请号：DE69016094

申请日：1990-04-23

Applicant: IBM

Inventor： EBBERS TIMOTHY JON ,  GUPTA SATISH ,  HENDERSON RANDALL LAWRENCE ,  HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM ,  WILLIAMS TODD

IPC: G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C7/00 ,  G11C11/409

Abstract: In a video random access memory which includes an implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out, a control signal is provided which causes the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers, resulting in an ability to select a stopping point when scanning out of the serial access memory, thereby allowing both the starting and ending points of the data to be scanned out of the serial access memory, to be specified.

公开(公告)号：DE3853511D1

公开(公告)日：1995-05-11

申请号：DE3853511

申请日：1988-09-19

Applicant: IBM

Inventor： ARANDA MICHAEL ARCHANGEL ,  EBBERS TIMOTHY JON ,  IIDA YOSHIO ,  KINDGREN TERENCE WALLACE ,  ROBERTSON TAGGART HUTH

IPC: G06T11/20 ,  G06T11/00

Abstract: A system for generating multiple pixels in a single machine cycle employs a plurality of parallel vector generators. Each of the parallel generators is initialized with an error term which is calculated in accordance with Bresenham's algorithm. The signs of these error terms are then used to determine the region within the first octant of the coordinate system which contains the function for which the pixels are to be generated. The region data, in turn, determine two selectable values for an increment which is to be added to a running error term for each of the parallel generators as multiple pixels are simultaneously generated. The choice of the two possible values to be added to the error term is dependent upon the sign of the error term itself. The sign of the running error term for each vector generator is utilized to form a sequence of binary data which represents the incremental changes in the pixel positions as the pixels are being generated. In a preferred embodiment, the binary data is translated into pixel position data which is then stored in a memory device. Any generated pixel data which cannot be stored in the machine cycle in which it is generated is re-routed for storage in later cycles.

公开(公告)号：SG42829A1

公开(公告)日：1997-10-17

申请号：SG1995002336

申请日：1990-10-17

Applicant: IBM

Inventor： EBBERS TIMOTHY JON

IPC: G06T11/00 ,  G06T1/00 ,  G06T17/00

Abstract: Video random access memory having a random array and serial buffer is employed to speed the replication of structure state information used in the processing of hierarchical graphic data structures. Specialized circuitry in the video RAM and associated VRAM sequencer are used to perform a rapid transfer of structure state information from one row of the VRAM (the parent row) to a second VRAM row (the child row). The sequencer is modified to perform back to back read data transfer and write data transfer operation in response to a single graphics processor command. The return to previous structure state can be accomplished by readdressing the VRAM row containing the previous structure state.

公开(公告)号：DE69030295T2

公开(公告)日：1997-09-18

申请号：DE69030295

申请日：1990-10-17

Applicant: IBM

Inventor： EBBERS TIMOTHY JON

IPC: G06T1/00 ,  G06T11/00 ,  G06T17/00

Abstract: Video random access memory having a random array and serial buffer is employed to speed the replication of structure state information used in the processing of hierarchical graphic data structures. Specialized circuitry in the video RAM and associated VRAM sequencer are used to perform a rapid transfer of structure state information from one row of the VRAM (the parent row) to a second VRAM row (the child row). The sequencer is modified to perform back to back read data transfer and write data transfer operation in response to a single graphics processor command. The return to previous structure state can be accomplished by readdressing the VRAM row containing the previous structure state.

公开(公告)号：DE3853511T2

公开(公告)日：1995-09-28

申请号：DE3853511

申请日：1988-09-19

Applicant: IBM

Inventor： ARANDA MICHAEL ARCHANGEL ,  EBBERS TIMOTHY JON ,  IIDA YOSHIO ,  KINDGREN TERENCE WALLACE ,  ROBERTSON TAGGART HUTH

IPC: G06T11/20 ,  G06T11/00

Abstract: A system for generating multiple pixels in a single machine cycle employs a plurality of parallel vector generators. Each of the parallel generators is initialized with an error term which is calculated in accordance with Bresenham's algorithm. The signs of these error terms are then used to determine the region within the first octant of the coordinate system which contains the function for which the pixels are to be generated. The region data, in turn, determine two selectable values for an increment which is to be added to a running error term for each of the parallel generators as multiple pixels are simultaneously generated. The choice of the two possible values to be added to the error term is dependent upon the sign of the error term itself. The sign of the running error term for each vector generator is utilized to form a sequence of binary data which represents the incremental changes in the pixel positions as the pixels are being generated. In a preferred embodiment, the binary data is translated into pixel position data which is then stored in a memory device. Any generated pixel data which cannot be stored in the machine cycle in which it is generated is re-routed for storage in later cycles.