公开(公告)号：DE69028382T2

公开(公告)日：1997-03-13

申请号：DE69028382

申请日：1990-10-10

Applicant: IBM

Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/409

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：AU630843B2

公开(公告)日：1992-11-05

申请号：AU6583090

申请日：1990-11-05

Applicant: IBM

Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

IPC: G11C11/401 ,  G11C11/4096 ,  G11C7/00

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：CA2074879A1

公开(公告)日：1993-05-01

申请号：CA2074879

申请日：1992-07-29

Applicant: IBM

Inventor： GRUNBOK WARREN W ,  KNOWLES BILLY J ,  MILANI WILLIAM R ,  MORAN DOUGLAS R ,  PONTIUS DALE E ,  PRICE DONALD W ,  TAMLYN ROBERT ,  TING YEE-MING ,  TRAN DE ,  YEH HENRY

IPC: G06F12/06 ,  G06F13/16 ,  G11C8/12 ,  G11C8/00

Abstract: KI9-91-010 MEMORY SYSTEM AND UNIQUE MEMORY CHIP ALLOWING ISLAND INTERLACE A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

公开(公告)号：CA2026461C

公开(公告)日：1993-03-09

申请号：CA2026461

申请日：1990-09-28

Applicant: IBM

Inventor： HILTEBEITEL NATHAN R ,  TAMLYN ROBERT ,  TOMASHOT STEVEN W

IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/40 ,  G11C11/34 ,  G11C11/409

Abstract: MULTIPLEXED SERIAL REGISTER ARCHITECTURE FOR VRAM A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：BR9006027A

公开(公告)日：1991-09-24

申请号：BR9006027

申请日：1990-11-28

Applicant: IBM

Inventor： HILTEBEITEL NATHAN R ,  TAMLYN ROBERT ,  TOMASHOT STEVEN W

IPC: G11C11/401 ,  G11C11/4096 ,  G11C15/00

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：DE69028382D1

公开(公告)日：1996-10-10

申请号：DE69028382

申请日：1990-10-10

Applicant: IBM

Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/409

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：DE69016697T2

公开(公告)日：1995-08-10

申请号：DE69016697

申请日：1990-04-23

Applicant: IBM

Inventor： GUPTA SATISH ,  HENDERSON RANDALL LAWRENCE ,  HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM ,  WILLIAMS TODD

IPC: G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/409

Abstract: A video random access memory includes an implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis, wherein the frame buffers are each stored in a portion of a row in a single video RAM, data from each of the two frame buffers is available following data transfer to the serial access memory register, a double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal, and the serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

公开(公告)号：DE69016094D1

公开(公告)日：1995-03-02

申请号：DE69016094

申请日：1990-04-23

Applicant: IBM

Inventor： EBBERS TIMOTHY JON ,  GUPTA SATISH ,  HENDERSON RANDALL LAWRENCE ,  HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM ,  WILLIAMS TODD

IPC: G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C7/00 ,  G11C11/409

Abstract: In a video random access memory which includes an implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out, a control signal is provided which causes the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers, resulting in an ability to select a stopping point when scanning out of the serial access memory, thereby allowing both the starting and ending points of the data to be scanned out of the serial access memory, to be specified.

公开(公告)号：AU6583090A

公开(公告)日：1991-06-13

申请号：AU6583090

申请日：1990-11-05

Applicant: IBM

Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

IPC: G11C11/401 ,  G11C11/4096 ,  G11C7/00

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：AT142365T

公开(公告)日：1996-09-15

申请号：AT90119442

申请日：1990-10-10

Applicant: IBM

Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/409

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.