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    2.
    发明专利
    未知

    公开(公告)号：DE69028382T2

    公开(公告)日：1997-03-13

    申请号：DE69028382

    申请日：1990-10-10

    Applicant: IBM

    Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

    IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/409

    Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

    MULTIPLEXED SERIAL REGISTER ARCHITECTURE FOR VRAM
    3.
    发明专利
    MULTIPLEXED SERIAL REGISTER ARCHITECTURE FOR VRAM 未知

    公开(公告)号：AU630843B2

    公开(公告)日：1992-11-05

    申请号：AU6583090

    申请日：1990-11-05

    Applicant: IBM

    Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

    IPC: G11C11/401 ,  G11C11/4096 ,  G11C7/00

    Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

    4.
    发明专利
    未知

    公开(公告)号：AT142365T

    公开(公告)日：1996-09-15

    申请号：AT90119442

    申请日：1990-10-10

    Applicant: IBM

    Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

    IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/409

    Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

    6.
    发明专利
    未知

    公开(公告)号：DE69016697D1

    公开(公告)日：1995-03-23

    申请号：DE69016697

    申请日：1990-04-23

    Applicant: IBM

    Inventor： GUPTA SATISH ,  HENDERSON RANDALL LAWRENCE ,  HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM ,  WILLIAMS TODD

    IPC: G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/409

    Abstract: A video random access memory includes an implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis, wherein the frame buffers are each stored in a portion of a row in a single video RAM, data from each of the two frame buffers is available following data transfer to the serial access memory register, a double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal, and the serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

    Multiplexed serial register architecture for VRAM
    7.
    发明专利
    Multiplexed serial register architecture for VRAM 未知

    公开(公告)号：HK120197A

    公开(公告)日：1997-09-05

    申请号：HK120197

    申请日：1997-06-26

    Applicant: IBM

    Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

    IPC: G11C11/4096 ,  G11C11/401 ,  G11C11/409

    Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

    8.
    发明专利
    未知

    公开(公告)号：ES2091783T3

    公开(公告)日：1996-11-16

    申请号：ES90119442

    申请日：1990-10-10

    Applicant: IBM

    Inventor： HILTEBEITEL NATHAN RAFAEL ,  TAMLYN ROBERT ,  TOMASHOT STEVEN WILLIAM

    IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/409

    Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

    Cached synchronous dram architecture having a mode register programmable cache policy
    10.
    发明专利
    Cached synchronous dram architecture having a mode register programmable cache policy 未知

    公开(公告)号：SG70607A1

    公开(公告)日：2000-02-22

    申请号：SG1997003013

    申请日：1997-08-21

    Applicant: IBM

    Inventor： ROGERS JIM LEWIS ,  TOMASHOT STEVEN WILLIAM

    IPC: G11C11/407 ,  G06F12/08 ,  G11C11/401 ,  G11C11/409 ,  G06F12/02 ,  G06F9/00

    Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.

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