公开(公告)号：WO2006027308A3

公开(公告)日：2006-05-11

申请号：PCT/EP2005053996

申请日：2005-08-15

Applicant: IBM ,  IBM UK ,  FAYAD CAMIL ,  LI JOHN ,  SUTTER SIEGFRIED

Inventor： FAYAD CAMIL ,  LI JOHN ,  SUTTER SIEGFRIED

IPC: G06F1/00

CPC classification number: G06F21/72 ,  G06F21/79

Abstract: An integrated circuit chip is provided which contains one or more processors and one or more cryptographic engines. A flow control circuit having a command processor accepts requests and data via a secure external interface through which only encrypted information is passed. The flow control circuit mediates decryption of this information using cryptographic keys that are present in hard coded form on the chip. In particular the flow control circuit includes a programmable hardware portion which is configurable in a secure manner to create a flexible internal chip architecture. The chip also includes a volatile memory disposed on a voltage island on which is maintained either through a battery backup or from a fixed power source (mains). The chip is thus enabled to securely perform cryptographic operations with the processors controlling the cryptographic engines through the flow control circuit.

Abstract translation: 提供一种集成电路芯片，其包含一个或多个处理器和一个或多个加密引擎。 具有命令处理器的流控制电路经由安全的外部接口接收请求和数据，通过该外部接口仅传递加密的信息。 流控制电路使用以硬编码形式存在于芯片上的加密密钥介入该信息的解密。 特别地，流控制电路包括可编程硬件部分，其可以以安全的方式配置以创建灵活的内部芯片架构。 该芯片还包括布置在电压岛上的易失性存储器，其上通过电池备份或从固定电源（电源）保持。 因此，芯片能够通过流量控制电路与控制密码引擎的处理器进行安全地执行加密操作。

公开(公告)号：JP2002236448A

公开(公告)日：2002-08-23

申请号：JP2001376593

申请日：2001-12-11

Applicant: IBM

Inventor： CHEN CHIN-LONG ,  CONDORELLI VINCENZO ,  FAYAD CAMIL

IPC: G06F7/72 ,  G09C1/00

Abstract: PROBLEM TO BE SOLVED: To generate a multiplier which multiples modulo N of two large integers. SOLUTION: A modular exponentiation function used for a public key encryption and decryption systems is actualized in a stand-alone engine which shares overlapping hardware structures and has as a core a modular multiplying circuit operating in two phases. For multiplication and addition, a large array in the hardware structure is partitioned into small structures and then a multiplier which includes a series of nearly identical elements linked together in a chained fashion can be designed. The overall structure can be operated in a pipelined fashion as a result of the two-phase operation and chaining of the partitioned processing elements, so that the throughput and speed are improved. The chained processing elements are so constituted as to provide a partitionable chain with separate parts for processing factors of a modulus.

公开(公告)号：JP2004004784A

公开(公告)日：2004-01-08

申请号：JP2003115786

申请日：2003-04-21

Applicant: IBM

Inventor： CONDORELLI VINCENZO ,  FAYAD CAMIL

IPC: G09C1/00 ,  H04L9/32

Abstract: PROBLEM TO BE SOLVED: To provide a method for generating a message digest. SOLUTION: The method comprises: a step for receiving a data block; and a step for processing the data block for obtaining the message digest. The step for obtaining the data block comprises computing of the data block at a time (t) based on a time (t-x). (x) is larger than or equal to 2. COPYRIGHT: (C)2004,JPO