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公开(公告)号：US5552591B1
公开(公告)日：2000-05-02
申请号：US2129893
申请日：1993-02-22
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , CHEN CHIN-LONG , DILL FREDERICK H , GOODMAN DOUGLAS S , HSIAO MU-YUE , MCCANN PAUL V , MULLIGAN JAMES M , RAND RICKY A
CPC classification number: G06K7/10861 , G06K1/126 , G06K7/0166 , G06K19/06028 , G06K2019/06253
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公开(公告)号：EP0097159A4
公开(公告)日：1985-07-01
申请号：EP82900591
申请日：1981-12-30
Applicant: IBM
Inventor： CHEN CHIN-LONG
CPC classification number: G06F11/1028
Abstract: A modularized error correction apparatus for correcting package errors is provided by expanding an N bit single error correction, double error detection code to cover N packages of M bits each, so that the Exclusive-OR of all M bit single bit error syndromes in any given package results in a composite syndrome which is unique for each package. See Fig. 2 for the parity matrix H and the matching matrix M for the error correction code.
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公开(公告)号：JP2002251137A
公开(公告)日：2002-09-06
申请号：JP2001376619
申请日：2001-12-11
Applicant: IBM
Inventor： CHEN CHIN-LONG , CONDORELLI VINCENZO , FOGELL LEONARD L
Abstract: PROBLEM TO BE SOLVED: To form a multiplier which multiplies two large integers modulo N. SOLUTION: A modula exponential function used for an open key ciphering and deciphering system is actualized by a stand-alone engine having as a core a modula multiplying circuit which shares an overlapping hardware structure and operates in two phases. For multiplication and addition, a large array in the hardware structure is sectioned into small structures and then a multiplier including a series of nearly identical processing elements linked in a chain can be designed. The whole structure becomes able to operate in a pipeline style as a result of the two-phase operation and chaining of the sectioned processing elements and the throughput and speed are improved. The chained processing elements are so constituted as to provide a chain which has individual parts processing factors of modulus and can be sectioned.
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4.发明专利
公开(公告)号：JP2002236448A
公开(公告)日：2002-08-23
申请号：JP2001376593
申请日：2001-12-11
Applicant: IBM
Inventor： CHEN CHIN-LONG , CONDORELLI VINCENZO , FAYAD CAMIL
Abstract: PROBLEM TO BE SOLVED: To generate a multiplier which multiples modulo N of two large integers. SOLUTION: A modular exponentiation function used for a public key encryption and decryption systems is actualized in a stand-alone engine which shares overlapping hardware structures and has as a core a modular multiplying circuit operating in two phases. For multiplication and addition, a large array in the hardware structure is partitioned into small structures and then a multiplier which includes a series of nearly identical elements linked together in a chained fashion can be designed. The overall structure can be operated in a pipelined fashion as a result of the two-phase operation and chaining of the partitioned processing elements, so that the throughput and speed are improved. The chained processing elements are so constituted as to provide a partitionable chain with separate parts for processing factors of a modulus.
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公开(公告)号：DE69127416D1
公开(公告)日：1997-10-02
申请号：DE69127416
申请日：1991-06-21
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MU-YUE , MULLIGAN JAMES MICHAEL
Abstract: A single width bidirectional bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
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Patent Agency Ranking
公开(公告)号：DE69026743D1
公开(公告)日：1996-06-05
申请号：DE69026743
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：BR9001126A
公开(公告)日：1991-03-05
申请号：BR9001126
申请日：1990-03-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU4939990A
公开(公告)日：1990-09-13
申请号：AU4939990
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69127416T2
公开(公告)日：1998-02-26
申请号：DE69127416
申请日：1991-06-21
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MU-YUE , MULLIGAN JAMES MICHAEL
Abstract: A single width bidirectional bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
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公开(公告)号：DE3882175T2
公开(公告)日：1994-01-27
申请号：DE3882175
申请日：1988-04-19
Applicant: IBM
Inventor： CHEN CHIN-LONG
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