公开(公告)号：US3646516A

公开(公告)日：1972-02-29

申请号：US3646516D

申请日：1970-04-15

Applicant: IBM

Inventor： FLINDERS MICHAEL ,  GARDNER PETER LYCETT ,  HALLETT MICHAEL HENRY ,  JONES JOHN W ,  MINSHULL JOHN FRANCIS ,  TAYLOR KEITH GRAHAM

IPC: G06F12/16 ,  G06F11/16 ,  G11C15/04 ,  G06F11/00

CPC classification number: G06F11/1625

Abstract: Error detection circuitry employs duplicate equal order binary registers and comparison circuitry for detecting and diagnosis of errors in data bits being transferred between the storage registers and a data bus.

公开(公告)号：DE2234192A1

公开(公告)日：1973-03-22

申请号：DE2234192

申请日：1972-07-12

Applicant: IBM

Inventor： GARDNER PETER LYCETT ,  LLEWELLYN ROGER JAMES

IPC: G06F9/38 ,  G06F15/16 ,  G06F15/80 ,  G06F9/18

公开(公告)号：DE2548720A1

公开(公告)日：1976-06-10

申请号：DE2548720

申请日：1975-10-31

Applicant: IBM

Inventor： GARDNER PETER LYCETT

IPC: G06F9/28 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/12

Abstract: A microprogram control unit comprises a microprogram store and an interactive processor processing the micro instructions issued by the microprogram store to produce expanded system control signals, at least some of the processing elements of the interactive processor being each responsible for producing a unique subset of control signals, no other processing element being directly involved in producing control signals in that subset. The processing elements may be self-sequencing stores, the micro instruction supplying the initial entry point for each store may be provided with its own automatic looping facility.

公开(公告)号：DE2234429A1

公开(公告)日：1973-03-29

申请号：DE2234429

申请日：1972-07-13

Applicant: IBM

Inventor： GARDNER PETER LYCETT

IPC: G06F7/501 ,  G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  G06F7/76 ,  G11C15/00 ,  G11C15/04

公开(公告)号：DE2261221A1

公开(公告)日：1973-06-28

申请号：DE2261221

申请日：1972-12-14

Applicant: IBM

Inventor： GARDNER PETER LYCETT ,  JONES JOHN WYN

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/18

公开(公告)号：DE2238687A1

公开(公告)日：1973-03-22

申请号：DE2238687

申请日：1972-08-05

Applicant: IBM

Inventor： GARDNER PETER LYCETT

IPC: G06F7/505 ,  G06F7/00 ,  G06F7/50 ,  G06F7/508 ,  G06F7/76 ,  G11C15/04

公开(公告)号：GB1281387A

公开(公告)日：1972-07-12

申请号：GB5724169

申请日：1969-11-22

Applicant: IBM

Inventor： GARDNER PETER LYCETT

IPC: G06F7/50 ,  G06F7/505 ,  G11C15/04 ,  H03K19/00

Abstract: 1281387 Transistor bi-stable circuits INTERNATIONAL BUSINESS MACHINES CORP 22 Nov 1969 57241/69 Heading H3T [Also in Division G4] An associative store comprises an array of two state (1, X) cells, one of the sates (the X state) being such that a mismatch signal is not generated when the cell is interrogated, irrespective of whether the interrogation is for binary " 1 " or binary " 0 ". In an embodiment, Fig. 2 (not shown), the cells consist of a single emitter junction transistor cross-coupled with a double emitter junction transistor. In the " X " state with the single emitter transistor conductive no current is passed to the sense line during an interrogation. In a second embodiment, Fig. 9 (not shown), the cells consist of two cross-coupled double emitter transistors. These cells have two modes of operation. In the first the cell functions as described above. In the second the cell functions as a normal 1, 0 associative cell with mismatch signals being developed in both states under the appropriate interrogation. The mode of the cells is determined by a bistabletrigger connected to each column of the store.