公开(公告)号：US3646516A

公开(公告)日：1972-02-29

申请号：US3646516D

申请日：1970-04-15

Applicant: IBM

Inventor： FLINDERS MICHAEL ,  GARDNER PETER LYCETT ,  HALLETT MICHAEL HENRY ,  JONES JOHN W ,  MINSHULL JOHN FRANCIS ,  TAYLOR KEITH GRAHAM

IPC: G06F12/16 ,  G06F11/16 ,  G11C15/04 ,  G06F11/00

CPC classification number: G06F11/1625

Abstract: Error detection circuitry employs duplicate equal order binary registers and comparison circuitry for detecting and diagnosis of errors in data bits being transferred between the storage registers and a data bus.

公开(公告)号：GB1186704A

公开(公告)日：1970-04-02

申请号：GB998968

申请日：1968-03-01

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES

IPC: G01R19/00 ,  G11C15/04

Abstract: 1,186,704. Transistor switching circuits. INTERNATIONAL BUSINESS MACHINES CORP. 1 March, 1968, No. 9989/68. Heading H3T. [Also in Division G4] In a selection circuit for selecting from an ordered set of electronic components, the next operable component to a component issuing a selection signal, a series-connected chain of impedances is provided with selection signal sense circuits of successive components of the set connected to successive nodes of the chain and a selection signal generator of each component connected to the same node as the sense circuit of the next component of the set, the sense circuit of each inoperable component presenting to a selection signal an impedance substantially greater than that of any impedance of the chain. Word storage locations W0, W1, W2 ... (Fig. 1) of an associative store have respective selector triggers (not shown) to control which locations participate in read and write operations. A " NEXT " operation causes any selector trigger, which is set, to energize the corresponding line 2 and set the selector trigger of the next non-defective word storage location via a generating circuit G, resistor chain R1, R2 ..., a sense circuit S, an AND gate 4 and a transfer trigger (not shown). Fig. 2 shows a generating circuit G(N) comprising long-tailed NPN transistor pair T1, T2, and a sense circuit S(N+ 1) comprising transistor T3, regulating transistor T4 and clamp circuit T5, T6. The sense circuit of a defective word storage location has had its disconnection switches D opened (or fuses blown) previously so the sense circuit presents a high impedance to the resistor chain R1, R2 ... and so is skipped. Each resistor R1, R2 ... may be replaced by two equal resistors in series, with their common terminal clamped. In this case the inverters I of Fig. 1 may be dispensed with so each word storage location can accept a signal through S and AND gate 4 and deliver one through G simultaneously. Each resistor in the chain can be replaced by a diode or a plurality of diodes in parallel. The invention can also be used for skipping defective packages in a series of packages of integrated circuitry used in turn for processing data.

公开(公告)号：DE2654568A1

公开(公告)日：1977-07-14

申请号：DE2654568

申请日：1976-12-02

Applicant: IBM

Inventor： BARCLAY DONALD JOHN ,  HALLETT MICHAEL HENRY

IPC: G02F1/17 ,  G02F1/163 ,  G09F9/30 ,  G09G3/38

公开(公告)号：DE2642205A1

公开(公告)日：1977-03-31

申请号：DE2642205

申请日：1976-09-20

Applicant: IBM

Inventor： BARCLAY DONALD JOHN ,  BIRD COLIN LEONARD ,  HALLETT MICHAEL HENRY ,  MINSHULL JOHN FRANCIS ,  OWEN CHARLES EDWARD ,  KIRKMAN DAVID HORROBIN

IPC: G04G9/00 ,  C25D11/00 ,  G02F1/163 ,  G09F9/30 ,  G09G3/16 ,  G09G3/19 ,  G09G3/38

Abstract: 1473772 Controlling light INTERNATIONAL BUSINESS MACHINES CORP 30 Sept 1975 39872/75 Heading G2F [Also in Division G5] In a display device comprising a transfer electrode El, a dump electrode E2 and a plurality of display electrode E3 immersed in a liquid electrolyte, a potential difference is first applied between electrodes E1 and E2 such as to deposit coloured material on E1, and subsequently a potential difference is applied between E1 and at least one electrode E3 so as effectively to transfer the coloured material to the selected electrode(s) E3. In Fig. 2, dot electrodes E3 are arranged in rows and columns, each column having a respective electrode E1 and E2 and the electrolyte being separated from that in adjacent columns by partitions 14 or by being contained in channels in a substrate. If the coloured material is such as to deposit at a cathode, it is initially deposited on selected electrode E1 by earthing the conductor 15 (FET 18, input T2) and by turning on selected FETs 19 to render corresponding electrode E2 positive. FETs 19 are controlled by a like array of bi-stables 23 forming an input/output register 24, AND gate 22 and control input Cl applied simultaneously with input T2. Subsequently an input T1 renders conductor 15 positive and, in the previously selected columns only, the coloured material is effectively transferred to the electrodes E3 of a selected row by activating the corresponding row input R2 (row conductor to earth). By repeating the process the array is scanned row sequentially. Non-linear resistances Z, e.g. oppositely poled diodes connected in parallel, are preferably provided between each electrode E1 and E3 and its row conductor. Erasure of the display is by turning on FETs 21 (input C2) and successively energizing terminals R1, or by short-circuiting the electrodes E3 to the dump electrode E2. The former erasure method may be used when the display requires refreshing to overcome dissipation of the coloured material by diffusion effects. The current between an electrode E2 and a coloured electrode E3 causes a current sense amplifier 27 to set the respective bi-stable 23 for a subsequent re-writing step. Partial or complete erasure of the display due to electrical read-out thereof may be counteracted similarly by applying sequential positive and negative current pulses across electrodes E2 and E3, the nett current being zero. During the positive pulse, terminal 29 is energized and the current between a written electrode and the electrode E2 produces an output from the amplifier 27, so that the following negative pulse restores the electrode E3 to its original written state. The device may also be constructed as a seven segment display.

公开(公告)号：GB1162109A

公开(公告)日：1969-08-20

申请号：GB5753666

申请日：1966-12-22

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY

IPC: G11C11/411 ,  G11C15/04 ,  G11C19/28 ,  H03K3/012 ,  H03K3/037 ,  H03K3/288

Abstract: 1,162,109. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORP. 22 Dec., 1966, No. 57536/66. Heading G4C. [Also in Division H3] A data store incorporates transistor bi-stable circuits of the type in which the collector and base electrodes of two transistors are crosscoupled and the circuits use transistors having two emitter electrodes or equivalent assemblies of transistors, the current in the conducting transistor normally passing through one emitter 6 or 7, designated the control emitter, so that the state of the circuit may be ascertained by diverting the current to the other emitter (7 or 9) designated the output emitter. Thus, by raising the potential of a control emitter, current, if flowing to the transistor, is diverted to the associated output emitter and may be detected in a sense circuit connected thereto (not shown). Writing may be effected by simultaneously raising the potential of a control emitter so as to divert the current to the output emitter and lowering the potential of the output emitter of the transistor so that it conducts. At the same time the potential of the other output emitter may be raised. Writing may alternatively be effected by applying to a control emitter a pulse that first goes negative and then positive (Fig. 3, not shown). The negative portion causes the corresponding transistor to conduct and the positive portion temporarily diverts the current to the output emitter without changing the state unless a positive pulse is also applied to the associated output emitter. The circuit is made more sensitive to writing if the potential of the supply line is simultaneously lowered or removed. The bi-stable circuits are arranged in a matrix as shown in Fig. 6, the control emitters being connected to word lines 7 and 9 and the output emitters being connected to sense column lines 6 and 8. In a contents addressable store, matching may be effected by applying the address to the word lines or alternatively by applying the complement of the address to the sense lines. Data may be transferred from one position to another in the same column. For example, a " 1 " from A 1 is transferred in inverse sense by applying a read pulse to the A 1 word line 7 to provide a write pulse in the sense line 8 which will write a " 0 " into B 1 or C 1 according to which is sensitized by lowering its supply voltage. Data may also be shifted to the right or left. Thus if a read-out pulse is applied to the upper line 7, the state of A 2 would be indicated on sense line 8. If simultaneously the lower line 7 is energized to re-set C 1 to " 0 " and gate 10 is opened, C 1 will receive the data from A 2 . Transfer to the left or right may be effected if gate 10 is as shown in Fig. 7. A data pulse being transferred causes transistor 15 to conduct, cutting off 16 and whichever of 11 or 12 was previously rendered conducting by left or right shift control signals. The rise of collector voltage at the corresponding collector provides the write pulse. Logic transfer of data may alternatively be effected. Thus if A 1 andB 1 are read out simultaneously into sense line 8 and C 1 is sensitized by lowering its collector supply voltage, then C 1 will be changed to the " 1 " state if A 1 and B 1 were both " 0." Alternatively if A 1 and B 1 are read out into sense line 6 and C 1 sensitized then a " 1 " will be written into C 1 if A 1 or B 1 is "0." Again, if A 1 and B 1 are opposite and are read into sense lines 6 and 8 simultaneously then C 1 if sensitized will become " 0 " if both are " 0 " and " 1 " if both are 1." If the sense bias lines 6 are connected diagonally instead of vertically then diagonal shifting may be effected without external gating (Fig. 8, not shown). In this case the complement is shifted.

公开(公告)号：FI67646C

公开(公告)日：1985-04-10

申请号：FI773913

申请日：1977-12-22

Applicant: IBM

Inventor： HALLETT MICHAEL HENRY ,  SOWTER BRIAN RAYMOND ,  HENEGHAN MICHAEL JAMES

IPC: G09G1/00 ,  G06F3/153 ,  G09G1/04 ,  G09G1/28 ,  G09G5/30 ,  H04N3/23 ,  H04N9/28

Abstract: A three color gun cathode ray tube has convergence correction signals derived from digital signals stored in a digital data store. The screen of the tube is divided into a plurality of areas and a digital correction signal derived for each area. The system is arranged so that when the three beams are scanning a particular area the digital correction signal associated with that area is read out from the digital store, passed through a digital to analog converter and then applied to the convergence coils of the tube.

公开(公告)号：DE2756763A1

公开(公告)日：1978-06-29

申请号：DE2756763

申请日：1977-12-20

Applicant: IBM

Inventor： BARCLAY DONALD JOHN ,  BIRD COLIN LEONARD ,  HALLETT MICHAEL HENRY ,  MARTIN DAVID HUGH

IPC: H04N5/66 ,  G02F1/163 ,  G09F9/30 ,  G09G3/38

Abstract: According to the disclosure, electrochromic display apparatus is provided, comprising, an electrolyte containing an electrochromic material, a plurality of display electrodes in the electrolyte, the display electrodes being connected in at least one group to enable selection of display electrodes, means for selecting at least some display electrodes, means to effect deposition of a visible coating of colored species derived from the electrochromic material onto the selected display electrodes, and means to effect deposition of an invisible coating of the colored species onto all unselected display electrodes, whereby the potentials of selected and unselected display electrodes are equalized.

公开(公告)号：GB1218407A

公开(公告)日：1971-01-06

申请号：GB1759770

申请日：1968-07-04

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES ,  LLEWELYN ROGER JAMES

IPC: G06F9/26 ,  G06F15/80 ,  G11C15/04

Abstract: 1,218,407. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 July, 1968, No. 17597/70. Divided out of 1,218,406. Heading G4A. In an electronic data processing system, logic and arithmetic functions are performed by table-look-up operations on stored function tables, there being a function store containing function tables, a work store arranged in operation to store operands, and a microprogramme store arranged in operation to emit micro-instructions each including an operation code, the function and work stores comprising respective decoders arranged to decode a part of the operation code particular to the store. The disclosure is essentially included in the parent.

公开(公告)号：GB1173367A

公开(公告)日：1969-12-10

申请号：GB2192067

申请日：1967-05-11

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY

IPC: G11C8/16 ,  G11C11/411

Abstract: 1,173,367. Circuits employing bi-stable magrietic elements; transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 11 May, 1967, No. 21920/67. Headings H3B and H3T. [Also in Division G4] A matrix store having bi-stable data storage elements coupled between word lines and sense lines is such that a signal on a sense line produced by interrogation of an element can be used to set any further element coupled to the same sense line and conditioned to respond, and when an element is so conditioned the propagation of the signal to elements further along the sense line is inhibited. Fig. 3 shows a single storage element at the intersection of a word line and a complementary pair of bit/sense lines. One of transistors T1, T2 is conducting to store a bit. For reading, the word line potential is raised, thus cutting-off that one of the transistors T3 corresponding to the conducting transistor T1 or T2, producing a pulse on the corresponding bit/sense line at the top of Fig. 3. For writing, a pulse is applied to that one of the bit/sense lines at the bottom of Fig. 3 corresponding to the complement of the bit value to be written, and the potential on the word line is lowered then raised to normal again. The pulse on the bit/sense line causes the corresponding transistor T4 to conduct. The transistor T1 or T2 corresponding to the other transistor T4 will conduct when the word line potential returns to normal. The lowering of the word line potential prevents the pulse arriving on one of the incoming bit/sense lines (bottom of Fig. 3) from passing along the outgoing bit/sense lines (top of Fig. 3), by disabling the transistors T3. Accordingly a word can be written either from external bit drivers or from another word position in the matrix, and the passage prevention feature of the previous sentence enables a plurality of words to be transferred simultaneously. A modification straightforwardly omits one of the pair of sense lines and the associated transistors T3, T4 &c. Transferring a word in true rather than complement form is also mentioned. Thin magnetic film stores are mentioned. Specification 1,119,357 is referred to for alternative storage elements.

公开(公告)号：GB1127270A

公开(公告)日：1968-09-18

申请号：GB4062367

申请日：1967-09-05

Applicant: IBM

Inventor： GARDNER PETER ALAN EDWARD ,  HALLETT MICHAEL HENRY ,  TITMAN PETER JAMES

IPC: G11C15/04 ,  H03K3/29

Abstract: 1,127,270. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORP. 5 Sept., 1967, No. 40623/67. Heading G4C. [Also in Division H3] A transistor binary storage cell, suitable for an associative store, provides the same first output signal whether it is in its " 1 " state and is interrogated for a "1" or is in its " 0 " state and is interrogated for a " 0 " and has a third state which also provides the first output signal whether it is interrogated for a " 0 " or " 1 ". The cell may have a fourth state which provides a different output signal when so interrogated. The storage cell in Fig. 4 comprises two bi-stable circuits arranged such that in state " 1 " T1 and T2 conduct, state " 0 " T1 and T3 conduct, state " 3 " T2 and T3 conduct and state " 4 " T1 and T4 conduct. Non - destructive interrogation for a " 0 " (i.e. a " 0 " match) is effected by switching the " 0 bit " a line 44 to - 0-2 V at switch 46 and the " 1 bit " line 45 to 0À1 V at switch 47. If the cell is in the " 0 " state transistor T1 is conducting but its emitter current is directed by the operation of switch 46 to emitter E12. T4 is non-conductive so that no current flows to the output line 43 from either transistor, indicating a " 0 " match. If however the circuit is in the " 1 " state the current from T4 is directed to the output line 43 indicating " no match ". Interrogating for a " 1 " match may be similarly effected and produces no current in line 43 if the match conditions exist. If the cell is in the third state neither transistor T1 nor T4 is conducting and no current flows to line 43, indicating "match" whether interrogation is for a " 0 " or a " 1 ". If however it is in the fourth state T1 and T4 both conduct and one or other current is directed to the output line 43 whether interrogation is for a " 0 " or " 1 ", indicating no match. Non-destructive read out may alternatively be effected by closing switch 49 on 0À1 V and switches 46 and 47 on 0 V. Current flowing from T1 or T4 into one or other of the bit lines 44 and 45 indicates the state of the circuit. Writing is effected by applying the interrogating voltage, such as from switches 46 and or/47, to the bit lines and lowering the threshold of the bi-stable circuits by closing switch 48 on the 2.0 V terminal and switch 49 on the 0À1 V terminal so that the transistors are into the conducting or non conducting states corresponding to the positions of switches 46 and 47. The previous state of the cell may first be destroyed by momentarily closing switch 48 on the floating terminal. If switch 49 is moved to the - 0À2 V terminal the data cell is isolated since the bit lines are then ineffective to direct the emitter currents to the output line 43. In Fig. 6 emitter followers are used in the cross couplings (as described with reference to Fig. 5, not shown) to avoid the necessity of hard saturation. In addition switch 48 is replaced by a switch 61 and the collectors of the emitter followers are taken to a tap on the collector resistors of the main transistors T1, T2, T3, T4. Interrogating and writing is carried out in a similar manner to Fig. 4 except that the lowering of the threshold to permit writing is effected by operating switch 61 to - V so as to increase the current through the emitter resistors and reduce the current through resistors R3b and R6b. Fig. 6 shows a circuit having only the first, second and third stable states, the states being represented by one of the main transistors T7, T8 or T9 conducting. These three transistors derive their input through respective emitter followers from the joint output of the other two main transistors so that any one of the main transistors will conduct only when the other two are non-conducting. Interrogating for a " 0 " is effected by placing such voltages on the bit lines 71 and 72 that if current is flowing in transistor T7 it is steered through emitter E71 to the " 0 " bit line to indicate match whereas if current is flowing in transistor T8 it is directed through emitter E82 to the word emitter line 73 to indicate no match. Interrogating for a " 1 " is similarly effected. If the circuit is in the third state (T9 conductive) no significant current reaches the output emitter lines 73 whichever interrogation is carried out and a match signal is indicated. A null interrogation is effected by placing such voltages on the bit lines that no significant current reaches the word emitter line even if T7 or T8 is conducting. Reading is effected by placing such a voltage on the word emitter line 73 that if current is flowing in transistors T7 or T8 it is diverted to the associated bit line to indicate the state of the cell. If T9 is conducting no current will appear on either line. Writing is effected by placing such a voltage on the word emitter line 73 that the switching threshold of transistors T7 and T8 is lowered and placing voltages on the bit lines 44, 45 such as to force the transistors T7 and T8 into the required conducting conditions. The cell is described in relation to an associative store (Fig. 1, not shown) in which the input register (11) is coupled to the columns of the store through a masking register (13). The cell enables one particular data position to be ignored without masking the whole of the column.