公开(公告)号：JP2000013407A

公开(公告)日：2000-01-14

申请号：JP13087499

申请日：1999-05-12

Applicant: IBM

Inventor： BLANC ALAIN ,  GOHL SYLVIE ,  SAUREL ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide buffer expansion architecture capable of efficiently combining the buffering abilities of respective switching modules. SOLUTION: Switchboad fabrics 10 and 20 are provided with the sets of switchboard core/access layer(SCAL) elements. The specified switchboard core is allocated to any arbitrary port adapter for regular cell traffic, and the other exchange core is provided as a means for reserving backup traffic or maintenance traffic conditions. The respective switchboard cores 15 and 25 are provided with mask mechanisms, control a routing process using a value loaded in a mask register and, ordinarily, change bit map values used in the switchboard cores 15 and 25. Since the mask registers in two switchboard cores are loaded with complementary values, only through one SCAL transmission element, the complete distribution of cells to the arbitrary port adapters is enabled.

公开(公告)号：DE69826640D1

公开(公告)日：2004-11-04

申请号：DE69826640

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE ,  GOHL SYLVIE ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.

公开(公告)号：DE69826640T2

公开(公告)日：2005-10-06

申请号：DE69826640

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE ,  GOHL SYLVIE ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.

公开(公告)号：DE69734968D1

公开(公告)日：2006-02-02

申请号：DE69734968

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  NICOLAS LAURENT ,  GOHL SYLVIE

IPC: H04L12/54 ,  H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit includes means for introducing at least one extra byte to every cell. The extra byte is reserved for carrying a routing header for controlling the switching structure in a first step, and then for use by the PINT circuit when the cell will be received by the transmit part in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells generated at the corresponding output port and controls whether to discard the cell based on the value of the extra byte.

公开(公告)号：DE69734968T2

公开(公告)日：2006-07-27

申请号：DE69734968

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  NICOLAS LAURENT ,  GOHL SYLVIE

IPC: H04L12/54 ,  H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit includes means for introducing at least one extra byte to every cell. The extra byte is reserved for carrying a routing header for controlling the switching structure in a first step, and then for use by the PINT circuit when the cell will be received by the transmit part in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells generated at the corresponding output port and controls whether to discard the cell based on the value of the extra byte.