公开(公告)号：WO0223816A8

公开(公告)日：2003-11-20

申请号：PCT/EP0110281

申请日：2001-09-06

Applicant: IBM ,  IBM FRANCE

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  GALLEZOT RENE ,  LE MAUT FRANCOIS ,  WIND DANIEL ,  ROMAN THIERRY

IPC: H04L12/18 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/56

CPC classification number: H04L49/201 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027

Abstract: The invention allows to assess a level of multicast traffic in a data switch of the kind devised to steer fixed-size data packets, from input to output ports, through a shared memory which temporarily holds a single copy of them in buffers. Output ports are each equipped with an output port queue which contains pointers to those of the buffers holding data packets due to leave the data switch through them. Then, the invention assumes that the total number of shared-memory buffers currently holding a data packet is counted and compared to the total number of buffer pointers found in the output queues. Hence, a metric of the level of multicast traffic is derived resulting in the calculation of a MultiCast Index (MCI). The invention further assumes that data switch is used together with a Switch Core Adaptation Layer (SCAL) which includes a multicast input queue. Because traffic is handled on the basis of a set of priority classes a multicast threshold MCT(P), associated to the multicast input queue, per priority, is set or updated. Therefore, while receiving incoming data traffic, MCI is kept calculated and, for each priority class (P), in each SCAL, MCI is compared to MCT(P) to determine whether corresponding multicast traffic must be held or not. The invention helps preventing traffic congestion in communications networks, using fixed-size data packet switches, that would otherwise occur when a high level of multicast and broadcast traffic has to be supported at network nodes.

Abstract translation: 本发明允许评估一种数据交换机中的组播流量级别，该数据交换机旨在通过共享存储器来引导固定大小的数据分组，该共享存储器暂时保存其缓冲器中的单个副本。 每个输出端口都配有一个输出端口队列，其中包含指向缓冲器的指针，这些缓冲器保留数据包，这是因为通过数据包进行数据交换。 然后，本发明假设当前保存数据分组的共享存储器缓冲器的总数被计数，并且与在输出队列中发现的缓冲器指针的总数进行比较。 因此，导出多播流量级别的度量，导致计算多卡通指数（MCI）。 本发明还假设数据交换与包括多播输入队列的交换机核心适配层（SCAL）一起使用。 由于基于一组优先级处理流量，所以设置或更新每个优先级与多播输入队列相关联的多播阈值MCT（P）。 因此，在接收传入数据业务的同时，保持计算MCI，并且对于每个SCAL中的每个优先级（P），将MCI与MCT（P）进行比较，以确定是否必须保持相应的组播流量。 本发明有助于防止在网络节点必须支持高级组播和广播流量时出现的固定大小的数据分组交换机，从而防止通信网络中的交通拥堵。

公开(公告)号：JP2000013407A

公开(公告)日：2000-01-14

申请号：JP13087499

申请日：1999-05-12

Applicant: IBM

Inventor： BLANC ALAIN ,  GOHL SYLVIE ,  SAUREL ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide buffer expansion architecture capable of efficiently combining the buffering abilities of respective switching modules. SOLUTION: Switchboad fabrics 10 and 20 are provided with the sets of switchboard core/access layer(SCAL) elements. The specified switchboard core is allocated to any arbitrary port adapter for regular cell traffic, and the other exchange core is provided as a means for reserving backup traffic or maintenance traffic conditions. The respective switchboard cores 15 and 25 are provided with mask mechanisms, control a routing process using a value loaded in a mask register and, ordinarily, change bit map values used in the switchboard cores 15 and 25. Since the mask registers in two switchboard cores are loaded with complementary values, only through one SCAL transmission element, the complete distribution of cells to the arbitrary port adapters is enabled.

公开(公告)号：DE3175351D1

公开(公告)日：1986-10-23

申请号：DE3175351

申请日：1981-10-28

Applicant: IBM ,  IBM FRANCE

Inventor： BREZZO BERNARD ,  CALVIGNAC JEAN ,  DAMBRICOURT RICHARD ,  MASCLET ANDRE ,  SANCHE JEAN-PIERRE

IPC: H04L69/14 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42

Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.

公开(公告)号：JP2000069052A

公开(公告)日：2000-03-03

申请号：JP3243799

申请日：1999-02-10

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L12/70 ,  H04L12/801 ,  H04L12/825 ,  H04L12/931 ,  H04L12/935 ,  H04L12/937 ,  H04L25/49 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide a flow control channel for switching architecture usable even at the time of attachment to a port expansion part. SOLUTION: Concerning the flow control method for switching architecture provided with a central switch core having a related distributed switch core access layer to communicate with a core through serial data communication links 40 and 50, the serial links 40 and 50 report coded data flows according to 8B/10B codes and prepare additional dedicated flow control channels while using two of three comma characters. In the idle or vacant state of cells, the kind of the comma character to first appear in the cell provides suitable flow control bit information.

公开(公告)号：JP2000013408A

公开(公告)日：2000-01-14

申请号：JP13102199

申请日：1999-05-12

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04L12/947 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide switching architecture for expanding the ability of a switchboard by utilizing the respective storage resources of a switching system. SOLUTION: A switching system 15 or 25 receives data cells from the set of (n) pieces of input ports, and according to the contents of a bit map value led into the cell at the entrance of a module, the cell is routed to output ports more than one. The module is provided with a shared buffer for storing the routed cell. Further, this system is provided with an additional mask mechanism having a mask register for changing the bit map value according to whether the concerned cell is to be moved to the output port or to be abandoned before that bit map value is used for controlling a routing process.

公开(公告)号：JP2004007848A

公开(公告)日：2004-01-08

申请号：JP2003326558

申请日：2003-09-18

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  DEBORD PIERRE ,  WIDMER ALBERT

IPC: H04J3/00 ,  H04L12/54 ,  H04L12/70 ,  H04L12/801 ,  H04L12/825 ,  H04L12/931 ,  H04L12/935 ,  H04L12/937 ,  H04L25/49 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide a flow control channel for switching architecture usable even when attached to a port expansion part. SOLUTION: The flow control method for switching architecture is provided with a central switch core having a related distributed switch core access layer to communicate with a core through serial data communication links, the serial links report coded data flows according to 8B/10B codes and prepare additional dedicated flow control channels while using two of three comma characters. In the idle or vacant state of cells, the kind of the comma character to first appear in the cell provides suitable flow control bit information. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000069004A

公开(公告)日：2000-03-03

申请号：JP3386299

申请日：1999-02-12

Applicant: IBM

Inventor： BLANC ALAIN ,  DEBORD PIERRE ,  SAUREL ALAIN ,  BREZZO BERNARD

IPC: H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/947 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide a flow control mechanism for which it is not necessary to add a control lead or wiring for sending various flow control signals for decelerating the speed of several components in a switching architecture. SOLUTION: At each input port (i), an SCAL element 1000 is provided with a reception protocol interface (PINT) 511 for processing a specified protocol corresponding to an adapter, to which the input port (i) is allocated, and a first sequential means 1160 for connection through a first serial communication link 1400 with a switch core. When a cell is received by the switch core, the cell is made non-sequential by a first non-sequential means 1170. At each output port, the cell is made sequential again by a second sequential means 1190 and next sent through a second serial communication link such as coaxial cable or optical cable to a suitable SCAL.

公开(公告)号：DE69826640D1

公开(公告)日：2004-11-04

申请号：DE69826640

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE ,  GOHL SYLVIE ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.

公开(公告)号：DE69817159D1

公开(公告)日：2003-09-18

申请号：DE69817159

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching system (15 or 25) receiving data cells from a set of n input ports and to be routed to one or more output ports in accordance with the contents of a bitmap value introduced in the cell at the entrance of said module, said module comprising a shared buffer for storing the cells which are to be routed. The systems further comprises a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process for either transporting the considered cell to the output port or discarding the latter. Two switching systems are combined in a first and a second Switch Fabrics (10, 20) in order to respectively form a first and second switch cores, located in a centralized building and a set of Switch Core Access Layer (S.C.A.L.) elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of one of said switching system. A set of Port Adapters (30; 31) are distributed at different physical areas and are connected to said first and second Switch Fabrics via a particular SCAL element so that each Switching system (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch cores. The mask achieves the distribution of the first and second switching systems between the different attached Port adapters, thus providing a load balancing between the two switching systems permitting to associate their individual buffering resources.

公开(公告)号：BR8206142A

公开(公告)日：1983-10-18

申请号：BR8206142

申请日：1982-10-21

Applicant: IBM

Inventor： BREZZO BERNARD ,  JEAN CALVIGNAC ,  DAMRICOURT RICHARD ,  MASCLET ANDRE ,  SANCHE JAN-PIERRE

IPC: H04L69/14 ,  G06F13/00 ,  G06F13/38 ,  G05B15/02

Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.