公开(公告)号：JP2000013408A

公开(公告)日：2000-01-14

申请号：JP13102199

申请日：1999-05-12

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04L12/947 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide switching architecture for expanding the ability of a switchboard by utilizing the respective storage resources of a switching system. SOLUTION: A switching system 15 or 25 receives data cells from the set of (n) pieces of input ports, and according to the contents of a bit map value led into the cell at the entrance of a module, the cell is routed to output ports more than one. The module is provided with a shared buffer for storing the routed cell. Further, this system is provided with an additional mask mechanism having a mask register for changing the bit map value according to whether the concerned cell is to be moved to the output port or to be abandoned before that bit map value is used for controlling a routing process.

公开(公告)号：JP2000069004A

公开(公告)日：2000-03-03

申请号：JP3386299

申请日：1999-02-12

Applicant: IBM

Inventor： BLANC ALAIN ,  DEBORD PIERRE ,  SAUREL ALAIN ,  BREZZO BERNARD

IPC: H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/947 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide a flow control mechanism for which it is not necessary to add a control lead or wiring for sending various flow control signals for decelerating the speed of several components in a switching architecture. SOLUTION: At each input port (i), an SCAL element 1000 is provided with a reception protocol interface (PINT) 511 for processing a specified protocol corresponding to an adapter, to which the input port (i) is allocated, and a first sequential means 1160 for connection through a first serial communication link 1400 with a switch core. When a cell is received by the switch core, the cell is made non-sequential by a first non-sequential means 1170. At each output port, the cell is made sequential again by a second sequential means 1190 and next sent through a second serial communication link such as coaxial cable or optical cable to a suitable SCAL.

公开(公告)号：JP2000013407A

公开(公告)日：2000-01-14

申请号：JP13087499

申请日：1999-05-12

Applicant: IBM

Inventor： BLANC ALAIN ,  GOHL SYLVIE ,  SAUREL ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE

IPC: H04L12/54 ,  H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide buffer expansion architecture capable of efficiently combining the buffering abilities of respective switching modules. SOLUTION: Switchboad fabrics 10 and 20 are provided with the sets of switchboard core/access layer(SCAL) elements. The specified switchboard core is allocated to any arbitrary port adapter for regular cell traffic, and the other exchange core is provided as a means for reserving backup traffic or maintenance traffic conditions. The respective switchboard cores 15 and 25 are provided with mask mechanisms, control a routing process using a value loaded in a mask register and, ordinarily, change bit map values used in the switchboard cores 15 and 25. Since the mask registers in two switchboard cores are loaded with complementary values, only through one SCAL transmission element, the complete distribution of cells to the arbitrary port adapters is enabled.

公开(公告)号：DE69826640D1

公开(公告)日：2004-11-04

申请号：DE69826640

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE ,  GOHL SYLVIE ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.

公开(公告)号：DE69817159D1

公开(公告)日：2003-09-18

申请号：DE69817159

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching system (15 or 25) receiving data cells from a set of n input ports and to be routed to one or more output ports in accordance with the contents of a bitmap value introduced in the cell at the entrance of said module, said module comprising a shared buffer for storing the cells which are to be routed. The systems further comprises a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process for either transporting the considered cell to the output port or discarding the latter. Two switching systems are combined in a first and a second Switch Fabrics (10, 20) in order to respectively form a first and second switch cores, located in a centralized building and a set of Switch Core Access Layer (S.C.A.L.) elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of one of said switching system. A set of Port Adapters (30; 31) are distributed at different physical areas and are connected to said first and second Switch Fabrics via a particular SCAL element so that each Switching system (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch cores. The mask achieves the distribution of the first and second switching systems between the different attached Port adapters, thus providing a load balancing between the two switching systems permitting to associate their individual buffering resources.

公开(公告)号：DE69737676T2

公开(公告)日：2008-01-10

申请号：DE69737676

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  SAUREL ALAIN ,  BREZZO BERNARD ,  PORET MICHEL

IPC: H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

公开(公告)号：DE69737676D1

公开(公告)日：2007-06-14

申请号：DE69737676

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  SAUREL ALAIN ,  BREZZO BERNARD ,  PORET MICHEL

IPC: H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

公开(公告)号：DE69826640T2

公开(公告)日：2005-10-06

申请号：DE69826640

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  ROBBE JEAN-CLAUDE ,  GOHL SYLVIE ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.

公开(公告)号：DE69817159T2

公开(公告)日：2004-05-06

申请号：DE69817159

申请日：1998-05-29

Applicant: IBM

Inventor： BLANC ALAIN ,  BREZZO BERNARD ,  SAUREL ALAIN

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A Switching system (15 or 25) receiving data cells from a set of n input ports and to be routed to one or more output ports in accordance with the contents of a bitmap value introduced in the cell at the entrance of said module, said module comprising a shared buffer for storing the cells which are to be routed. The systems further comprises a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process for either transporting the considered cell to the output port or discarding the latter. Two switching systems are combined in a first and a second Switch Fabrics (10, 20) in order to respectively form a first and second switch cores, located in a centralized building and a set of Switch Core Access Layer (S.C.A.L.) elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of one of said switching system. A set of Port Adapters (30; 31) are distributed at different physical areas and are connected to said first and second Switch Fabrics via a particular SCAL element so that each Switching system (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch cores. The mask achieves the distribution of the first and second switching systems between the different attached Port adapters, thus providing a load balancing between the two switching systems permitting to associate their individual buffering resources.