公开(公告)号：DE19847245A1

公开(公告)日：1999-07-22

申请号：DE19847245

申请日：1998-10-14

Applicant: IBM

Inventor： HAAS JUERGEN ,  HALLER WILHELM DR ,  KRAUCH ULRICH ,  LUDWIG THOMAS ,  WETTER HOLGER

IPC: G06F7/50 ,  G06F7/575 ,  G06F7/02 ,  G08C19/00

Abstract: The two operands (A,B) are fed to a carry network (30) and a partial sum arithmetic unit (32) that contains a bit function generator (42) and a sum generator. The outputs are fed to a result selector (70) that consists of AND logic (72- 92) and three multiplexers (M1-M3).

公开(公告)号：DE19846828A1

公开(公告)日：1999-05-20

申请号：DE19846828

申请日：1998-10-10

Applicant: IBM

Inventor： HALLER WILHELM DR ,  KRAUCH ULRICH ,  LUDWIG THOMAS ,  WETTER HOLGER

IPC: G06F7/491 ,  G06F7/50

Abstract: The combined binary decimal adder has summing logic coupled to decimal point carry logic. The unit contains correction logic (24,26) that acts upon different operands and introduces a +6 and -6 correction values. An initial sum logic unit (36,38) generates for each decimal position corrected operands. Outputs are fed to multiplexers (M5-M8).