公开(公告)号：DE10110576A1

公开(公告)日：2001-10-11

申请号：DE10110576

申请日：2001-03-06

Applicant: IBM

Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

IPC: G01R31/3185 ,  G06F11/26

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

公开(公告)号：DE10110576B4

公开(公告)日：2008-06-12

申请号：DE10110576

申请日：2001-03-06

Applicant: IBM

Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

IPC: G06F11/26 ,  G01R31/3185

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.