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    VLSI CIRCUIT AND MANUFACTURE THEREOF
    1.
    发明专利
    VLSI CIRCUIT AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2000068276A

    公开(公告)日：2000-03-03

    申请号：JP10858599

    申请日：1999-04-15

    Applicant: IBM

    Inventor： ASUM HESSEL ,  ERICH KLINK ,  JUERGEN KEHR ,  WENDEL DIETER ,  PASOTAM TORIKAM PATEL

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To obtain a VLSI(very large scale integration) circuit which reduces crosstalks between metal planes and in the metal plane of the VLSI circuit, and manufacture thereof. SOLUTION: One metal plane i+1 of a VLSI chip has a wiring 1, disposed according to the design of the chip and empty regions which have no wiring between metal lines. Channels which are not used in the empty regions are buried by voltage/ground lines 7 connected to a nearby plane (not shown). These segments are connected to voltage/ground buses 9 on a nearby plane i. The added voltage tracks and ground tracks shield wirings oriented in the same direction, to abruptly lessen the in-plane inter-line couplings or crosstalks. In addition, the inter-line coupling between vertical planes reduces approximately down to zero.

    WRITE/READ DEVICE FOR MEMORY CELL AND ITS METHOD
    2.
    发明专利
    WRITE/READ DEVICE FOR MEMORY CELL AND ITS METHOD 失效

    公开(公告)号：JPH1069772A

    公开(公告)日：1998-03-10

    申请号：JP19820797

    申请日：1997-07-24

    Applicant: IBM

    Inventor： BUETTNER STEFAN ,  PILLE JUERGEN ,  WENDEL DIETER ,  WERNICKE FRIEDRICH

    IPC: G11C11/41 ,  G11C11/419

    Abstract: PROBLEM TO BE SOLVED: To provide a new method restoring a bit line and a data line from a memory cell. SOLUTION: All bit lines (510, 511) and all data lines (517, 518) are connected during a restoration operation, and all restored FET (503, 504, 505) are used for supplying a required recharging current. Successively a non-address specified bit line is turned off by its bit switch. Thus, a size of a recharging device can be made considerably small.

    Methods and apparatus for operating master and slave latches
    3.
    发明专利
    Methods and apparatus for operating master and slave latches 有权
    用于操作主机和从机锁的方法和装置

    公开(公告)号：JP2005080295A

    公开(公告)日：2005-03-24

    申请号：JP2004244947

    申请日：2004-08-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： WARNOCK JAMES D ,  WENDEL DIETER

    IPC: H03K3/3562 ,  G06F1/06 ,  H03K3/037

    CPC classification number: G06F1/06 ,  H03K3/0372

    Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for operating master and slave latches. SOLUTION: In a first embodiment, a method for operating a master latch and a slave latch coupled to the master latch is provided. The method includes steps of attempting to operate the master latch and the slave latch in a first mode in which (1) the master latch is held in an open condition; and (2) the slave latch is pulsed so as to latch data passed through the open master latch. If the master latch and the slave latch do not operate in the first mode, the master latch and the slave latch are operated in a second mode in which (1) a first clock signal is employed to latch data with the master latch; and (2) a second clock signal is employed to latch data latched by the master latch with the slave latch. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供用于操作主从锁存器的方法和装置。 解决方案：在第一实施例中，提供了一种用于操作耦合到主锁存器的主锁存器和从锁存器的方法。 该方法包括以第一模式操作主锁存器和从锁存器的步骤，其中（1）主锁存器保持在打开状态; 和（2）从锁存器被脉冲以锁定通过打开的主锁存器的数据。 如果主锁存器和从锁存器不在第一模式下操作，则主锁存器和从锁存器在第二模式下操作，其中（1）使用第一时钟信号来与主锁存器锁存数据; 和（2）第二时钟信号用于锁存由主锁存器锁存的数据与从锁存器。 版权所有（C）2005，JPO＆NCIPI

    METHOD AND DEVICE FOR DETERMINING PRIORITY IN CYCLIC BUFFER
    4.
    发明专利
    METHOD AND DEVICE FOR DETERMINING PRIORITY IN CYCLIC BUFFER 失效

    公开(公告)号：JPH10254677A

    公开(公告)日：1998-09-25

    申请号：JP3480198

    申请日：1998-02-17

    Applicant: IBM

    Inventor： SOELL WERNER ,  WENDEL DIETER ,  WERNICKE FRIEDRICH-CHRISTIAN

    IPC: G06F5/06 ,  G06F5/10 ,  G06F7/74

    Abstract: PROBLEM TO BE SOLVED: To inhibit a selected entry which has no priority by determining the priority of an entry in a cyclic buffer wherein an entry should meet given reference with respect to a cyclic buffer which includes a sequence of entries. SOLUTION: An in pointer 103 and an out pointer 104 are provided which allow the cyclic buffer 100 to operate as an FIFO buffer. When the cyclic buffer 110 is full, the in pointer 105 defines the head of a stored entry sequence. In contrast, the tail of the entry sequence is defined by the out pointer 106 which indicates the 1st occupied entry position which is the oldest entry position of the sequence of entry positions. An entry determined by the out pointer 106 is selected each time an entry of the FIFO which should exit from the FIFO is selected. Then the out pointer 106 id increased and a new unoccupied entry position becomes usable.

    6.
    发明专利
    未知

    公开(公告)号：DE10110576B4

    公开(公告)日：2008-06-12

    申请号：DE10110576

    申请日：2001-03-06

    Applicant: IBM

    Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

    IPC: G06F11/26 ,  G01R31/3185

    Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

    7.
    发明专利
    未知

    公开(公告)号：DE10110578B4

    公开(公告)日：2004-06-03

    申请号：DE10110578

    申请日：2001-03-06

    Applicant: IBM

    Inventor： LEENSTRA JENS ,  MUELLER ANTJE ,  PILLE JUERGEN ,  WENDEL DIETER

    IPC: G06F13/18 ,  G06F13/26 ,  G06F7/00

    Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.

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