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    Checkpointing of superscalar out-of-order processor for error recovery
    1.
    发明专利
    Checkpointing of superscalar out-of-order processor for error recovery 有权
    检查超级失调处理器的错误恢复

    公开(公告)号：JP2003067184A

    公开(公告)日：2003-03-07

    申请号：JP2002185571

    申请日：2002-06-26

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： BAROWSKI HARRY STEFAN DR ,  SCHWERMER HARTMUT DR ,  TAST HANS-WERNER

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/38 ,  G06F11/14

    CPC classification number: G06F9/3842 ,  G06F9/30174 ,  G06F9/3834 ,  G06F9/3863 ,  G06F9/3885

    Abstract: PROBLEM TO BE SOLVED: To provide a data processing system having a built-in error recovery from a given check point. SOLUTION: For checkpointing a plurality of instruction in every one cycle, updating of designated maximum register contents executed by a plurality of CISC/RISC instructions is collected in a buffer (CSB) 60 for a check point condition, whereby the check point condition includes buffer slots of the same number as that of registers to be updated by the plurality of CISC instructions, and an item of a program counter value related to the youngest external instruction of the plurality of CISC instructions. After it is determined that no error is detected in the register data, before the completion of the youngest external instruction of the plurality of external instructions or at the completion thereof, the already architected register array (ARA) 64 is updated by newly collected register data.

    Abstract translation: 要解决的问题：提供从给定检查点具有内置错误恢复的数据处理系统。 解决方案：为了在每一个周期内检查多个指令，由多个CISC / RISC指令执行的指定的最大寄存器内容的更新被收集在用于检查点条件的缓冲器（CSB）60中，由此检查点条件包括缓冲器 与由多个CISC指令更新的寄存器的编号相同的时隙，以及与多个CISC指令的最小外部指令相关的程序计数器值的项目。 在确定在寄存器数据中没有检测到错误之后，在完成多个外部指令中最年轻的外部指令之前，或在完成时，已经构建的寄存器阵列（ARA）64被新收集的寄存器数据 。

    DEVICE FOR EXECUTING SUB-ROUTINE CALLING AND RETURN OPERATION AND METHOD THEREFOR
    2.
    发明专利
    DEVICE FOR EXECUTING SUB-ROUTINE CALLING AND RETURN OPERATION AND METHOD THEREFOR 失效

    公开(公告)号：JPH11259298A

    公开(公告)日：1999-09-24

    申请号：JP925899

    申请日：1999-01-18

    Applicant: IBM

    Inventor： HILGENDORF ROLF ,  LAUB OLIVER ,  TAST HANS-WERNER

    IPC: G06F9/38 ,  G06F9/42 ,  G06F12/0875

    Abstract: PROBLEM TO BE SOLVED: To reduce a processing time for defining the target address of a sub-routine return instruction. SOLUTION: In a computer having a processor equipped with an instruction prefetch mechanism including a branch history table for storing the target address of plural branch instructions to be found in an instruction stream, a sub-routine calling and return operation is executed. In this case, the branch history table 22 includes a latent calling instruction tag and a return instruction tag. Each time the latent sub-routine calling instruction is found in the prefetch instruction stream, a pair of addresses including the calling target address of the instruction and the next successive instruction address are stored in a return identification stack 24. Then, a detected branch instruction activates associative retrieval for the next successive instructing part identifying the branch instruction as the return instruction by a matched entry in the return identification stack. Then, a pair of addresses included in the matched entry are transferred to a return cache 30 provided in parallel to the branch history table.

    INFORMATION TRANSMISSION BUS AND METHOD
    3.
    发明专利
    INFORMATION TRANSMISSION BUS AND METHOD 失效

    公开(公告)号：JPH10105308A

    公开(公告)日：1998-04-24

    申请号：JP23564297

    申请日：1997-09-01

    Applicant: IBM

    Inventor： GOLDRIAN GOTTFRIED ,  TAST HANS-WERNER

    IPC: G06F3/00 ,  G06F13/42 ,  H04L12/40

    Abstract: PROBLEM TO BE SOLVED: To transmit a time critical command to a transmission partner while watching a time limit and to use an optimum bus line relating to a transmission band width by switching a bus between an initial state and a second state. SOLUTION: In the initial state of the bus, a data transmission direction is scheduled from a unit A to the unit B for a half bus 211, that is one segment of the bus line, and data are transmitted from the unit B to the unit A in the half bus 212, that is the other segment of the bus line. As a transmitted function, by making a transmission direction invertible in the half bus 211 (212), the bus is converted from the initial state to the entire band width. That is, in the case that the large amount of the data are transmitted from the unit A to the unit B, even though the transmission direction of the half bus 211 is not changed (213), the transmission direction of the half bus 212 is changed (214). Thereafter, the data transmission direction of the half bus 214 is inverted again.

    Managing fetch and store requests in a cache pipeline
    4.
    发明专利
    Managing fetch and store requests in a cache pipeline 未知

    公开(公告)号：GB2456405A

    公开(公告)日：2009-07-22

    申请号：GB0822457

    申请日：2008-12-10

    Applicant: IBM

    Inventor： JACOBI CHRISTIAN ,  FABEL SIMON ,  PFLANZ MATTHIAS ,  TAST HANS-WERNER ,  ULRICH HANNO

    IPC: G06F12/08 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0893

    Abstract: In a cache accessed under the control of a cache pipeline (14), store requests are managed in a store queue (10) and read requests are managed in a read queue (12), respectively, and prioritization logic (18) decides if a read request or a write request is to be forwarded to the cache pipeline (14). The prioritization logic (62) aborts a store request that has started if a fetch request arrives within a predetermined store abort window and grants cache access to the arrived fetch request. When the fetch request no longer requires the input stage of the cache pipeline, a control mechanism repeats the access control of the aborted store request for a further trial to access the pipeline (14). Preferably, the store abort window spans 3 to 7 cycles, preferably 4 or 5 cycles, and starts after 2 to 4 cycles, preferably 3 cycles.

    L2 Cache memory
    6.
    发明专利
    L2 Cache memory 未知

    公开(公告)号：DE19614481A1

    公开(公告)日：1997-10-16

    申请号：DE19614481

    申请日：1996-04-12

    Applicant: IBM

    Inventor： WILLE UDO ,  GETZLAFF KLAUS-JOERG ,  WITHELM BIRGIT ,  TAST HANS-WERNER

    IPC: G06F12/0897 ,  G06F12/08 ,  G06F13/16 ,  G06F15/16

    Abstract: The second order cache memory (L2) has a directory (9) which stores an address i and validity bit Vi(L1) for each of its memory sectors Yi. The value of each validity bit depends on whether the contents of sector Yi are also stored in the corresponding sector Zj of a first order cache memory (L1). Both cache memories store the V-, MC- and C-bits used for MESI cache protocol.

    10.
    发明专利
    未知

    公开(公告)号：DE69122860T2

    公开(公告)日：1997-04-03

    申请号：DE69122860

    申请日：1991-07-06

    Applicant: IBM

    Inventor： TAST HANS-WERNER ,  PFLUEGER THOMAS ,  GETZLAFF KLAUS JOERG DIPL ING

    IPC: G06F7/00 ,  G06F7/76 ,  H03K17/00 ,  H03M7/00 ,  H04J3/04

    Abstract: A multiplexer circuit is described which is built up from a series of smaller submultiplexers (241-247, 251-254). It selects a number of adjacent bits, bytes or words from one register and places them in the same order in a second register. The multiplexer can be used in cache memories or instruction buffers.

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