公开(公告)号：BR7702822A

公开(公告)日：1978-04-04

申请号：BR7702822

申请日：1977-05-02

Applicant: IBM

Inventor： HOOD R ,  BIRNEY R ,  DAVIS M

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/14 ,  G06F15/16 ,  G06F15/177 ,  G06F21/24 ,  G05B19/10

公开(公告)号：BR7702820A

公开(公告)日：1978-04-04

申请号：BR7702820

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY R ,  HOOD R

IPC: G06F12/06 ,  G06F12/14 ,  G05B19/10

Abstract: The disclosure describes equate operand spaces (EOS) control over the addressabilities accessed by means of different address keys in an address key register (AKR) in a processor. Executing instructions, and their source and sink type operands may have different address keys in the AKR, and therefore different addressabilities. When enabled, the EOS control forces each source operand fetch to occur within the sink operand addressability specified in the AKR, even though the AKR explicitly contains a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKR stores whether the EOS state is enabled or disabled in the processor.

公开(公告)号：BR7702780A

公开(公告)日：1978-02-21

申请号：BR7702780

申请日：1977-04-27

Applicant: IBM

Inventor： HOOD R ,  DAVIS M ,  BIRNEY R

IPC: G06F12/06 ,  G06F12/14 ,  G11C7/00 ,  H01H43/08

Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).

公开(公告)号：BR7708707A

公开(公告)日：1979-07-24

申请号：BR7708707

申请日：1977-12-28

Applicant: IBM

Inventor： HOOD R ,  DAVIS M ,  MAYES G

IPC: G06F9/305 ,  G06F9/34 ,  G06F12/04 ,  G06F3/00

Abstract: A method of accessing variable-length bit fields in the memory of an electronic data processing system irrespective of the relationship between the boundaries of addressable elements within said memory and the start and end of the bit fields comprising the operations of: setting the initial values of a base register within said system to contain a representation of a base address of an addressable element; setting the initial values of a shift register within said system to contain a representation of the offset in said memory of the beginning of a particular bit field from said base address; combining the contents of said base and offset registers in such a way as to provide a representation of the position in said memory of the first bit of said particular bit field; create a single instruction that contains a representation of the length of said particular bit field. (Machine-translation by Google Translate, not legally binding)

公开(公告)号：BR7702779A

公开(公告)日：1978-02-21

申请号：BR7702779

申请日：1977-04-29

Applicant: IBM

Inventor： HOOD R ,  DAVIS M ,  BIRNEY R

IPC: G06F12/14 ,  G06F12/02 ,  G06F9/06 ,  H01H43/08