公开(公告)号：DE3675129D1

公开(公告)日：1990-11-29

申请号：DE3675129

申请日：1986-08-22

Applicant: IBM

Inventor： IYER SUBRAMANIAN SRIKANTESWARA ,  JOSHI RAJIV VASANT

IPC: H01L21/3205 ,  C23C16/02 ,  C23C16/04 ,  C23C16/06 ,  C23F4/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/60

Abstract: Metal, such as tungsten, contact regions for an integrated circuit are deposited on exposed portions of a silicon substrate having an apertured silicon dioxide layer thereon by the steps of: …… (1) disposing the substrate in a deposition chamber; … (2) introducing a gaseous compound of a metal into the chamber, which compound reacts with silicon so that metal from the compound substitutes for silicon in the surface of the substrate to form a deposited metal layer in the apertures in the silicon dioxide layer; and … (3) introducing hydrogen into the chamber in addition to the gaseous compound whereby the hydrogen reacts with the gaseous compound to form a further deposition of the metal, the metal being deposited during said further deposition on the surface of both the previously deposited metal layer and the silicon dioxide layer. …… During step (3) an etching gas (e.g nitrogen trifluoride) which etches the metal when activated, is introduced into the chamber and a plasma struck to activate the etching gas. By controlling the amount of the etching gas introduced into the chamber and the electrical power coupled into the plasma, the silicon surface portions of the substrate are kept substantially free of the metal and a further deposit of the metal is produced on the previously deposited metal layer.

公开(公告)号：DE3869181D1

公开(公告)日：1992-04-23

申请号：DE3869181

申请日：1988-03-04

Applicant: IBM

Inventor： IYER SUBRAMANIAN SRIKANTESWARA ,  STORK JOHANNES MARIA CORNELIS

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/203 ,  H01L21/331 ,  H01L21/762 ,  H01L29/732 ,  H01L21/76 ,  H01L21/285

Abstract: A process for fabricating a bipolar transistor structure having device and isolation regions fully self-aligned. The transistor is fabricated using a process wherein collector (12), base (14) and emitter (16) layers are sequentially formed on a semiconductor substrate (10) by a molecular beam epitaxy technique. The emitter layer is covered by insulation layers and a photoresist layer is then formed on the insulation layer. The photoresist layer is masked, exposed and developed to provide a pattern which is used as an etch mask to form both the device emitter area (26) and isolation areas (28). The isolation areas (28), the emitter region (26) and the base (14) and collector (12) regions are therefore formed.

公开(公告)号：DE3370247D1

公开(公告)日：1987-04-16

申请号：DE3370247

申请日：1983-11-03

Applicant: IBM

Inventor： IYER SUBRAMANIAN SRIKANTESWARA

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/49 ,  H01L29/60 ,  H01L21/28