中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.019 seconds)

    SOFT METAL CONDUCTOR AND FORMING METHOD THEREFOR
    1.
    发明专利
    SOFT METAL CONDUCTOR AND FORMING METHOD THEREFOR 审中-公开

    公开(公告)号：JP2004006768A

    公开(公告)日：2004-01-08

    申请号：JP2003091887

    申请日：2003-03-28

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT ,  TEJWANI MANU JAMNADAS

    IPC: H01L21/28 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/43

    Abstract: PROBLEM TO BE SOLVED: To provide a soft metal conductor where hardness on an uppermost surface without abrasion is improved after the surface is polished by a chemical mechanical polishing process. SOLUTION: The soft metal conductor 78 has an uppermost layer composed of particles having sufficiently large particle sizes so that the surface without abrasion is obtained after polishing in the chemical mechanical polishing step and the conductor is used for a semiconductor device. Metallic particles having the particle sizes of 200nm or above are bonded to the uppermost layer in a conductive soft metal structure. COPYRIGHT: (C)2004,JPO

    Semiconductor circuit for leakage current mitigation and method of detecting and mitigating leakage current runaway
    2.
    发明专利
    Semiconductor circuit for leakage current mitigation and method of detecting and mitigating leakage current runaway 有权
    用于泄漏电流减小的半导体电路和漏电流电流检测和减轻的方法

    公开(公告)号：JP2011015396A

    公开(公告)日：2011-01-20

    申请号：JP2010142690

    申请日：2010-06-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOSHI RAJIV VASANT ,  YANG ZHIJIAN ,  GUO JONG-RU ,  WANG PING-CHUAN ,  HSU LOUIS LU-CHEN

    IPC: H03K5/08 ,  H01L21/822 ,  H01L27/04 ,  H03F1/52

    CPC classification number: H03K17/0822

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for mitigating a leakage current of a semiconductor device before catastrophic leakage current runaway occurs.SOLUTION: A leakage current shift monitor unit 20 is electrically connected to an output node of a leakage current target unit 10 and collects leakage currents from a selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator 40 receives and compares the outputs of the current shift monitor unit 20 and a reference voltage generator 30. The comparator 40 propagates an alert signal to the leakage current target unit 10 when the leakage voltage output from the leakage current shift monitor unit 20 exceeds the reference voltage, that is, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal attains leak mitigation also including a repair voltage to be applied to a gate of the target semiconductor device.

    Abstract translation: 要解决的问题：提供一种在灾难性漏电流失控之前减轻半导体器件的漏电流的装置和方法。解决方案：泄漏电流移动监视器单元20电连接到漏电流目标单元10的输出节点 并从所选择的目标半导体器件收集泄漏电流两个连续的预定义时间周期，并测量所收集的漏电流之间的差异。 比较器40接收并比较当前移动监视器单元20和参考电压发生器30的输出。当从泄漏电流移动监视单元20输​​出的泄漏电压超过时，比较器40向泄漏电流目标单元10传播报警信号 参考电压，即表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号还实现泄漏减轻，还包括要施加到目标半导体器件的栅极的修复​​电压。

    Level shifter for boosting wordline voltage and memory cell performance
    4.
    发明专利
    Level shifter for boosting wordline voltage and memory cell performance 有权
    提高字线电压和存储单元性能的级别更换

    公开(公告)号：JP2009118466A

    公开(公告)日：2009-05-28

    申请号：JP2008252263

    申请日：2008-09-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOSHI RAJIV VASANT ,  DHONG SANG HOO ,  JUERGEN PILLE ,  OSAMU TAKAHASHI ,  SCOTT RAYMOND COTTIER

    IPC: H03K19/0185 ,  H01L21/82 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

    CPC classification number: G11C8/08 ,  G11C11/418

    Abstract: PROBLEM TO BE SOLVED: To provide a level shifter for boosting a wordline voltage and memory cell performance without making a circuit defective in operation or without causing excessive leakage. SOLUTION: A circuit and a method include a first circuit powered by a first supply voltage and second a circuit powered by a second supply voltage. A level shifter is coupled between the first circuit and the second circuit. The level shifter is configured so that a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage is selected according to an input signal which depends on at least one of an operation to be performed and a component performing the operation. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于提高字线电压和存储单元性能的电平移位器，而不会使电路在操作中有缺陷或不引起过度泄漏。 解决方案：电路和方法包括由第一电源电压供电的第一电路，以及由第二电源电压供电的第二电路。 电平移位器耦合在第一电路和第二电路之间。 电平移位器被配置为使得根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，该输入信号取决于要执行的操作和执行操作的组件中的至少一个 操作。 版权所有（C）2009，JPO＆INPIT

    6.
    发明专利
    未知

    公开(公告)号：DE3675129D1

    公开(公告)日：1990-11-29

    申请号：DE3675129

    申请日：1986-08-22

    Applicant: IBM

    Inventor： IYER SUBRAMANIAN SRIKANTESWARA ,  JOSHI RAJIV VASANT

    IPC: H01L21/3205 ,  C23C16/02 ,  C23C16/04 ,  C23C16/06 ,  C23F4/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/60

    Abstract: Metal, such as tungsten, contact regions for an integrated circuit are deposited on exposed portions of a silicon substrate having an apertured silicon dioxide layer thereon by the steps of: …… (1) disposing the substrate in a deposition chamber; … (2) introducing a gaseous compound of a metal into the chamber, which compound reacts with silicon so that metal from the compound substitutes for silicon in the surface of the substrate to form a deposited metal layer in the apertures in the silicon dioxide layer; and … (3) introducing hydrogen into the chamber in addition to the gaseous compound whereby the hydrogen reacts with the gaseous compound to form a further deposition of the metal, the metal being deposited during said further deposition on the surface of both the previously deposited metal layer and the silicon dioxide layer. …… During step (3) an etching gas (e.g nitrogen trifluoride) which etches the metal when activated, is introduced into the chamber and a plasma struck to activate the etching gas. By controlling the amount of the etching gas introduced into the chamber and the electrical power coupled into the plasma, the silicon surface portions of the substrate are kept substantially free of the metal and a further deposit of the metal is produced on the previously deposited metal layer.

    SEMICONDUCTOR DEVICE AND WAFER STRUCTURE HAVING A PLANAR BURIED INTERCONNECT BY WAFER BONDING
    8.
    发明专利
    SEMICONDUCTOR DEVICE AND WAFER STRUCTURE HAVING A PLANAR BURIED INTERCONNECT BY WAFER BONDING 未知

    公开(公告)号：CA2105039C

    公开(公告)日：1996-10-29

    申请号：CA2105039

    申请日：1993-08-27

    Applicant: IBM

    Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOSHI RAJIV VASANT ,  SHEPARD JOSEPH FRANCIS

    IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L21/44 ,  H01L21/441 ,  H01L21/48

    Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

    9.
    发明专利
    未知

    公开(公告)号：DE3781312D1

    公开(公告)日：1992-10-01

    申请号：DE3781312

    申请日：1987-04-03

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT

    IPC: H01L21/3205 ,  H01L23/52 ,  H01L21/31

    Abstract: A method for fabricating a structure, which includes a layer (2) containing a refractory metal and a substrate (3) to which the refractory metal-containing layer does not strongly adhere, there being a thin bonding layer (5) between the substrate (3) and the refractory metal-containing layer (2) for providing good adherence between the refractory metal-containing layer and the substrate. The bonding layer (5) is an oxide, nitride or mixed osy-nitride layer initially prepared to be Si-rich in a surface region thereof. Inclusions (7) of the refractory metal are produced in the bonding layer (5) by substituting the refractory metal for excess free silicon (6) therein. These inclusions become nucleation and bonding sites for refractory metal deposition, ensuring good adhesion.

    10.
    发明专利
    未知

    公开(公告)号：DE69529775D1

    公开(公告)日：2003-04-03

    申请号：DE69529775

    申请日：1995-07-05

    Applicant: IBM

    Inventor： JOSHI RAJIV VASANT ,  TEJWANI MANU JAMNADAS ,  SRIKRISHNAN KRIS VENKATRAMAN

    IPC: H01L21/28 ,  H01L21/203 ,  H01L21/205 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

    Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH4 gas followed by WF6 can be used to produce an in-situ hard cap of WxGey. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450 DEG C) without degrading the underlying metals.

Patent Agency Ranking