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    CIRCUIT MODULE INCORPORATING A LOGIC ARRAY
    1.
    发明专利
    CIRCUIT MODULE INCORPORATING A LOGIC ARRAY 未知

    公开(公告)号：ZA7502023B

    公开(公告)日：1976-11-24

    申请号：ZA7502023

    申请日：1975-04-01

    Applicant: IBM

    Inventor： JONES JOHN WYN ,  JOHN WYN JONES

    IPC: G06F7/00 ,  G06F7/57 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/40 ,  G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  H03K

    CPC classification number: G06F11/2051 ,  G06F9/223 ,  G06F9/26 ,  G06F9/4484

    Abstract: A universal array logic module featuring autonomous operation includes interconnected array structured logic and a small writable storage array. The module is subject to large scale integrated packaging as a standardly dimensioned unit (e.g. chip). The internal connections form discrete first and second internal circulation loops in one of which the storage array connects as a serial constituent randomly addressable by signals carried in the other loop. The storage array typically holds eight 32-bit words. The logic arrays may be read-only structures organized to perform arithmetic and translational logic manipulations under autonomous (internal) control. The module assembly includes integral input/output gating for transferring signals between an external bus and the internal loops. The logic array structure permits both external and internal control of cyclic operation. The operation repertoire includes interrupts, resets, and sequence branches. Interrupted status (loop signals) is saved in predetermined address locations of the storage array, requiring novel manipulation and storage of the address argument of the interrupted cycle. The logic arrays may be economically configured as read-only structures.

    CIRCUIT MODULE INCORPORATING A LOGIC ARRAY
    3.
    发明专利
    CIRCUIT MODULE INCORPORATING A LOGIC ARRAY 未知

    公开(公告)号：ZA752023B

    公开(公告)日：1976-11-24

    申请号：ZA752023

    申请日：1975-04-01

    Applicant: IBM

    Inventor： JONES JOHN WYN ,  JOHN WYN JONES

    IPC: G06F7/57 ,  G06F7/00 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/40 ,  G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  H03K

    Abstract: A universal array logic module featuring autonomous operation includes interconnected array structured logic and a small writable storage array. The module is subject to large scale integrated packaging as a standardly dimensioned unit (e.g. chip). The internal connections form discrete first and second internal circulation loops in one of which the storage array connects as a serial constituent randomly addressable by signals carried in the other loop. The storage array typically holds eight 32-bit words. The logic arrays may be read-only structures organized to perform arithmetic and translational logic manipulations under autonomous (internal) control. The module assembly includes integral input/output gating for transferring signals between an external bus and the internal loops. The logic array structure permits both external and internal control of cyclic operation. The operation repertoire includes interrupts, resets, and sequence branches. Interrupted status (loop signals) is saved in predetermined address locations of the storage array, requiring novel manipulation and storage of the address argument of the interrupted cycle. The logic arrays may be economically configured as read-only structures.

    4.
    发明专利
    未知

    公开(公告)号：DE2517356A1

    公开(公告)日：1975-11-06

    申请号：DE2517356

    申请日：1975-04-19

    Applicant: IBM

    Inventor： JONES JOHN WYN

    IPC: G06F7/00 ,  G06F7/57 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/40 ,  G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  G06F13/06 ,  G11C8/00

    Abstract: A universal array logic module featuring autonomous operation includes interconnected array structured logic and a small writable storage array. The module is subject to large scale integrated packaging as a standardly dimensioned unit (e.g. chip). The internal connections form discrete first and second internal circulation loops in one of which the storage array connects as a serial constituent randomly addressable by signals carried in the other loop. The storage array typically holds eight 32-bit words. The logic arrays may be read-only structures organized to perform arithmetic and translational logic manipulations under autonomous (internal) control. The module assembly includes integral input/output gating for transferring signals between an external bus and the internal loops. The logic array structure permits both external and internal control of cyclic operation. The operation repertoire includes interrupts, resets, and sequence branches. Interrupted status (loop signals) is saved in predetermined address locations of the storage array, requiring novel manipulation and storage of the address argument of the interrupted cycle. The logic arrays may be economically configured as read-only structures.

    CATHODE RAY TUBE CONTROLLER
    7.
    发明专利
    CATHODE RAY TUBE CONTROLLER 未知

    公开(公告)号：DE3373579D1

    公开(公告)日：1987-10-15

    申请号：DE3373579

    申请日：1983-06-30

    Applicant: IBM

    Inventor： JONES JOHN WYN ,  THOMAS VINCENT PHILIP

    IPC: G06F3/153 ,  G09G1/16 ,  G09G5/00 ,  G09G5/08 ,  G09G5/18

    Abstract: A cathode-ray tube controller uses a content addressable associative storage array (10) to generate repetitively a sequence of video control signals for a CRT to which it is attached. A binary coded counter (4) incremented by the system clock (CL) of the CRT provides a sequence of binary count values representing the running count of the CRT clock. This running count is continuously available and applied as an input search argument to the associative array. A plurality of predetermined count values, derived with reference to the running count, are stored as binary coded words in selected rows of the associative array. The match signals generated on the sense lines of the array as the running count value becomes equal to the predetermined count values in the array provide the video control signals to control the various display functions of the CRT. One of the signals is used to re-set the running count value so that the sequence of signals is repeated at regular intervals. The timing of the video control signals is determined solely by the running count values entered into store. An input data register (15) is provided in order to load words into the array to define or to change the functions of display. A read register (17) is provided in which interrogated words are read for test and event timing purposes.

    CIRCUIT MODULE INCORPORATING A LOGIC ARRAY
    9.
    发明专利
    CIRCUIT MODULE INCORPORATING A LOGIC ARRAY 未知

    公开(公告)号：AU8003975A

    公开(公告)日：1976-10-14

    申请号：AU8003975

    申请日：1975-04-10

    Applicant: IBM

    Inventor： JONES JOHN WYN

    IPC: G06F7/00 ,  G06F7/57 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/40 ,  G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  G06F1/00 ,  H03K19/20

    Abstract: A universal array logic module featuring autonomous operation includes interconnected array structured logic and a small writable storage array. The module is subject to large scale integrated packaging as a standardly dimensioned unit (e.g. chip). The internal connections form discrete first and second internal circulation loops in one of which the storage array connects as a serial constituent randomly addressable by signals carried in the other loop. The storage array typically holds eight 32-bit words. The logic arrays may be read-only structures organized to perform arithmetic and translational logic manipulations under autonomous (internal) control. The module assembly includes integral input/output gating for transferring signals between an external bus and the internal loops. The logic array structure permits both external and internal control of cyclic operation. The operation repertoire includes interrupts, resets, and sequence branches. Interrupted status (loop signals) is saved in predetermined address locations of the storage array, requiring novel manipulation and storage of the address argument of the interrupted cycle. The logic arrays may be economically configured as read-only structures.

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