公开(公告)号：DE69303764T2

公开(公告)日：1997-02-06

申请号：DE69303764

申请日：1993-04-22

Applicant: IBM

Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOST MARK EDWIN ,  OGURA SEIKI NMN OGURA SEIKI NM ,  SCHULZ RONALD NORMAN

IPC: H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786 ,  H01L21/82 ,  H01L21/304

Abstract: A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000 ANGSTROM and bipolar devices formed in a thick epitaxial layer of 1 mu m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000 ANGSTROM over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 mu m in the bipolar regions and a 1000 ANGSTROM thick layer of epitaxial silicon in the CMOS regions.

公开(公告)号：DE69303764D1

公开(公告)日：1996-08-29

申请号：DE69303764

申请日：1993-04-22

Applicant: IBM

Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOST MARK EDWIN ,  OGURA SEIKI NMN OGURA SEIKI NM ,  SCHULZ RONALD NORMAN

IPC: H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786 ,  H01L21/82 ,  H01L21/304

Abstract: A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000 ANGSTROM and bipolar devices formed in a thick epitaxial layer of 1 mu m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000 ANGSTROM over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 mu m in the bipolar regions and a 1000 ANGSTROM thick layer of epitaxial silicon in the CMOS regions.