公开(公告)号：DE69303764T2

公开(公告)日：1997-02-06

申请号：DE69303764

申请日：1993-04-22

Applicant: IBM

Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOST MARK EDWIN ,  OGURA SEIKI NMN OGURA SEIKI NM ,  SCHULZ RONALD NORMAN

IPC: H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786 ,  H01L21/82 ,  H01L21/304

Abstract: A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000 ANGSTROM and bipolar devices formed in a thick epitaxial layer of 1 mu m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000 ANGSTROM over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 mu m in the bipolar regions and a 1000 ANGSTROM thick layer of epitaxial silicon in the CMOS regions.

公开(公告)号：DE69303332T2

公开(公告)日：1997-01-23

申请号：DE69303332

申请日：1993-04-19

Applicant: IBM

Inventor： CURRIE JAMES EDWARD ,  SCHULZ RONALD NORMAN ,  TICKNOR ADAM DAN

IPC: B23Q3/08 ,  B24B37/30 ,  H01L21/304 ,  B24B37/04

Abstract: A wafer polishing fixture is disclosed containing a first liquid film (6) confined by a non-porous but flexible enclosure (2,8) for distributing evenly the applied polishing forces across the surface of a wafer (7) supported by the confined liquid (6). The fixture comprises a flexible, non-porous template (2) with a pocket (5) for receiving a wafer (7) to be polished. A washer (4) is placed between a carrier (3) and the template pocket (5). A film of water (6) fills the bottom of the pocket (5) and is confined with the aid of the washer (4) and by an overlying porous pad (9) extending across the pocket (5) and having a non-porous sheath (8) facing the liquid (6). A second liquid film (10) saturates and covers the upper surface of the pad (9). The wafer (7) to be polished floats upon the second liquid film (10) within the pocket (5).

公开(公告)号：DE69303332D1

公开(公告)日：1996-08-01

申请号：DE69303332

申请日：1993-04-19

Applicant: IBM

Inventor： CURRIE JAMES EDWARD ,  SCHULZ RONALD NORMAN ,  TICKNOR ADAM DAN

IPC: B23Q3/08 ,  B24B37/30 ,  H01L21/304 ,  B24B37/04

Abstract: A wafer polishing fixture is disclosed containing a first liquid film (6) confined by a non-porous but flexible enclosure (2,8) for distributing evenly the applied polishing forces across the surface of a wafer (7) supported by the confined liquid (6). The fixture comprises a flexible, non-porous template (2) with a pocket (5) for receiving a wafer (7) to be polished. A washer (4) is placed between a carrier (3) and the template pocket (5). A film of water (6) fills the bottom of the pocket (5) and is confined with the aid of the washer (4) and by an overlying porous pad (9) extending across the pocket (5) and having a non-porous sheath (8) facing the liquid (6). A second liquid film (10) saturates and covers the upper surface of the pad (9). The wafer (7) to be polished floats upon the second liquid film (10) within the pocket (5).

公开(公告)号：DE69303764D1

公开(公告)日：1996-08-29

申请号：DE69303764

申请日：1993-04-22

Applicant: IBM

Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOST MARK EDWIN ,  OGURA SEIKI NMN OGURA SEIKI NM ,  SCHULZ RONALD NORMAN

IPC: H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786 ,  H01L21/82 ,  H01L21/304

Abstract: A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000 ANGSTROM and bipolar devices formed in a thick epitaxial layer of 1 mu m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000 ANGSTROM over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 mu m in the bipolar regions and a 1000 ANGSTROM thick layer of epitaxial silicon in the CMOS regions.

公开(公告)号：DE3468586D1

公开(公告)日：1988-02-11

申请号：DE3468586

申请日：1984-10-19

Applicant: IBM

Inventor： LAI FANG-SHI JORDAN ,  SCHULZ RONALD NORMAN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/306

Abstract: This invention relates to a process for forming deep trenches in semiconductor substrates by Reactive Ion Etching and more particularly relates to an etching process which prevents lateral etching or "blooming" in a heavily doped semiconductor region which is sandwiched by upper and lower lightly doped regions of semiconductor. Still more particularly it relates to an RIE process wherein the upper region is reactively ion etched in an atmosphere of CC 2 F 2 and argon to at least a portion of the thickness of the upper region and wherein any remaining thickness of the upper region, the heavily doped region and at least a portion of the lower region are reactively ion etched in an atmosphere of CCl 2 F 2 and oxygen to provide a trench with uniform sidewalls.