公开(公告)号：JP2007200303A

公开(公告)日：2007-08-09

申请号：JP2006351591

申请日：2006-12-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DR CEDRIC LICHTENAU ,  MARTIN RECKTENWALD ,  SCHMIDT ANDREAS ,  PFLUEGER THOMAS ,  KUENZER JENS ,  ROLF HILGENDORF B

IPC: G06F1/04 ,  G06F1/08

CPC classification number: G06F1/14 ,  G04F10/04 ,  H03L7/06

Abstract: PROBLEM TO BE SOLVED: To provide a system, a device, and a method of providing an accurate time-based counter for scaling an operating frequency of a microprocessor. SOLUTION: This system, this device, and this method make use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of a clock generation circuit of the microprocessor and is used to be fed to external and internal timebase logic and a timebase accumulator counter. The timebase accumulator counter accumulates tick events from the timebase logic between two core clocks. The accumulated value is transferred to a core clock domain on every clock edge of a scalable clock, and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种系统，设备和提供用于缩放微处理器的工作频率的精确的基于时间的计数器的方法。 解决方案：该系统，该装置和该方法利用基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL并且被用于馈送到 外部和内部时基逻辑和时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器被复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：GB2519359A

公开(公告)日：2015-04-22

申请号：GB201318518

申请日：2013-10-21

Applicant: IBM

Inventor： LICHTENAU CEDRIC ,  KUENZER JENS ,  GLOEKLER TILMAN ,  KOENIG ANDREAS

IPC: G06F11/22 ,  G01R31/28 ,  G06F11/27 ,  G11C29/12

Abstract: Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. The test lines having scan-in lines 22 and/or control lines 24. The interception means are responsive to the generation means in order to feed the generated scan-in data into each of the scan chains for initializing the electronic circuit. The test structure may input the scan-in data in parallel into the scan chains. The interception means may intercept the scan-in lines and the control lines, and the generation means may fetch pre-configured data from a memory for feeding into the scan-in lines. Also disclosed is a method of initialising the electronic circuit.