公开(公告)号：GB2456618A

公开(公告)日：2009-07-22

申请号：GB0822285

申请日：2008-12-08

Applicant: IBM

Inventor： KOENIG ANDREAS ,  KLEIN MATTHIAS ,  WALZ MANFRED ,  BUECHNER THOMAS

IPC: G06F11/07

Abstract: Disclosed is a method and circuit for operating self-checking logic 16, 18, 28 in a computer processing chip 10. The chip has functional units for detecting errors 28, for tracing the errors 18, and for controlling the processor clock 16, such that a clock-stop signal is generated by the self-checking logic which is used for error management and recovery. When a stop-clock signal is generated the signal is intercepted 440, a delay 445 is defined during which error-related, chip internal error handling and/ or recovery preparation actions are processed 470. At the end of the predetermined delay 460 the clock-stop action is performed 490, 495. A warning message to firmware may be sent to help in error and recovery management. The delay may be configured according to the location of the failure, the time needed to communicate with the stop-clock signal to the clock mechanism on the chip and/or the time needed to collect and store debug data.

公开(公告)号：GB2519359A

公开(公告)日：2015-04-22

申请号：GB201318518

申请日：2013-10-21

Applicant: IBM

Inventor： LICHTENAU CEDRIC ,  KUENZER JENS ,  GLOEKLER TILMAN ,  KOENIG ANDREAS

IPC: G06F11/22 ,  G01R31/28 ,  G06F11/27 ,  G11C29/12

Abstract: Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. The test lines having scan-in lines 22 and/or control lines 24. The interception means are responsive to the generation means in order to feed the generated scan-in data into each of the scan chains for initializing the electronic circuit. The test structure may input the scan-in data in parallel into the scan chains. The interception means may intercept the scan-in lines and the control lines, and the generation means may fetch pre-configured data from a memory for feeding into the scan-in lines. Also disclosed is a method of initialising the electronic circuit.

公开(公告)号：DE102014101633A1

公开(公告)日：2014-11-20

申请号：DE102014101633

申请日：2014-02-11

Applicant: IBM

Inventor： KOENIG ANDREAS ,  LICHTENAU CEDRIC ,  LOBO PREETHAM M ,  BROCK BISHOP ,  GLOEKLER TILMAN

IPC: G06F9/50

Abstract: Die Erfindung stellt einen IC-Chip (102) bereit, aufweisend ein Servicemodul (104), das so ausgelegt ist, dass eine oder mehrere Komponenten (114, 116, 118, 120) des Chips über eine oder mehrere Aufgaben (T1 bis T5) verwaltet werden, wobei das Servicemodul aufweist: – ein Verarbeitungsmodul (106); – einen Datenspeicher (112), auf dem ein gegenwärtiger Zustand (CS) einer gegenwärtig ausgeführten (T4) der Aufgaben gespeichert ist; – eine Schnittstelle (122) zum Empfangen einer Anforderung (R), um eine weitere (T1) der Aufgaben auszuführen, wobei die gegenwärtig ausgeführte Aufgabe (T4) eine erste Priorität (P4) aufweist und die andere Aufgabe (T1) eine zweite Priorität (P1) aufweist; – einen Taktgeber (108), der zum Messen eines Zeitintervalls ausgelegt ist, das zwischen dem Empfangen der Anforderung und der aktuellen Uhrzeit vergangen ist; – ein Steuermodul, das so ausgelegt ist, dass die gegenwärtig ausgeführte Aufgabe unterbrochen und die Ausführung der angeforderten Aufgabe ausgelöst wird, falls a) die zweite Priorität (P1) höher als die erste Priorität ist, und b1) der gespeicherte gegenwärtige Zustand anzeigt, dass die gegenwärtige Aufgabe ordnungsgemäß unterbrechbar ist; und/oder b2) das gemessene Zeitintervall einen Schwellenwert überschreitet, wodurch bei b2) die Unterbrechung und das Auslösen unabhängig davon ausgeführt werden, ob die gegenwärtig ausgeführte Aufgabe ordnungsgemäß beendet werden kann oder bereits ordnungsgemäß beendet wurde.

公开(公告)号：GB2455010B

公开(公告)日：2012-02-01

申请号：GB0822774

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  KOENIG ANDREAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER ,  WALZ MANFRED

IPC: G06F11/07

公开(公告)号：GB2466222B

公开(公告)日：2013-11-13

申请号：GB0822763

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  ZILLES GERHARD ,  WALZ MANFRED ,  GENTNER THOMAS ,  WAGNER ANDREAS ,  KOENIG ANDREAS

IPC: G06F9/50 ,  G06F11/07 ,  G06F13/20 ,  H04L12/841

公开(公告)号：GB2466222A

公开(公告)日：2010-06-16

申请号：GB0822763

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  ZILLES GERHARD ,  WALZ MANFRED ,  GENTNER THOMAS ,  WAGNER ANDREAS ,  KOENIG ANDREAS

IPC: G06F11/00 ,  G06F9/50 ,  G06F13/20 ,  H04L12/56

Abstract: Disclosed is a system for managing the resources processing data transfers in a transaction based input/output chip of a computer system. A transaction is associated with a resource, 18 the transaction being a request packet and a corresponding response packet. The system has a transaction table 10 for holding one resource for each request until the resource has been processed and a resource management 12 for storing information about the availability of these resources, which has become available before a predetermined timeout period T has been exceeded. The system has a FIFO (first-in first-out) memory 14 for buffering those resources, which have been made available after the first timeout period and a second timeout period Q have been exceeded. An arbiter circuit 16 for chooses the resources from the resource management, if any are available, if not the timed-out resources from the FIFO memory are used.

公开(公告)号：GB2456403A

公开(公告)日：2009-07-22

申请号：GB0822313

申请日：2008-12-08

Applicant: IBM

Inventor： KOENIG ANDREAS ,  SCHLIPF THOMAS ,  KLEIN MATTHIAS ,  WALZ MANFRED ,  FRITZ ROLF

IPC: G06F11/07

Abstract: A method of operating self-testing logic in a tree-like multi-chip processor cluster which generates an infrastructure signal 430, such as a clockstop or tracestop signal, used for error management and recovery. The operation intercepts 440 the infrastructure signal of a processor of the cluster then extracts error information from the infrastructure signal. Using the error information a pre-defined inter-chip error synchronisation scheme is selected 450 including clock-stop and/or trace-stop information for a respective one of the processors of the cluster. Notification signals are distributed 490 to chips of the cluster using dedicated wires or a low-level standard interface for chip-to-chip communication to prepare and execute error related internal operations for chips. On receipt of one of the notification signals a chip performs at least one of (i) performing a trace-stop command or (ii) performing a clock-stop command 495 on a respective one of the chips as derived from the synchronisation scheme. The synchronisation scheme may comprise a configurable delay adjustable according to the location of the failure within the chip.

公开(公告)号：GB2514126A

公开(公告)日：2014-11-19

申请号：GB201308598

申请日：2013-05-14

Applicant: IBM

Inventor： LICHTENAU CEDRIC ,  LOBO PREETHAM M ,  BROCK BISHOP ,  GLOEKLER TILMAN ,  KOENIG ANDREAS

IPC: G06F9/48

Abstract: An integrated circuit contains a service engine, which receives requests to execute tasks on a service processor. The tasks are assigned priorities. The state of the currently executing task indicates whether it can be interrupted without affecting its processing. When a request to execute a new task is received, the priority of the new task is compared with the priority of the currently executing task. If the currently executing task has a higher priority, it continues to execute. Otherwise, the engine waits a predetermined time. If, within that time, the executing task indicates that it can be interrupted, the executing task is terminated and the new task executed. If at the end of that time, the executing task has not indicated that it can be interrupted, it is terminated anyway and the new task is executed.

公开(公告)号：GB2455010A

公开(公告)日：2009-06-03

申请号：GB0822774

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  KOENIG ANDREAS ,  FRITZ ROLF

IPC: G06F11/07

Abstract: A method/apparatus for controlling an error handling procedure in a digital circuit with control logic comprises a plurality of control logic circuits 20 grouped into a number of error handling domains 26, 28. Each error handling domain 26, 28 is associated with a predetermined data flow of the digital circuit. The digital circuit comprises an extended error reporting unit 24 for receiving an indication of an error 30 in the control logic. The extended error reporting unit 24 includes a mask system for mapping the single errors onto error handling procedures. The digital circuit comprises an error handling unit 22 for performing the operations of the error handling procedure on the according component of the digital circuit. The control logic circuits could be implemented using finite state machines. This error handling system enables all errors to be handled using well-tested error handling procedures instead of being handled locally.