公开(公告)号：EP2033213A4

公开(公告)日：2012-08-01

申请号：EP07757974

申请日：2007-03-06

Applicant: IBM

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  B05D3/00 ,  C23C16/34 ,  C23C16/505 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

公开(公告)号：JP2005217400A

公开(公告)日：2005-08-11

申请号：JP2005011467

申请日：2005-01-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  DORIS BRUCE B ,  GHALI ROMANY ,  GLUSCHENKOV OLEG G ,  GRIBELYUK MICHAEL A ,  LEE WOO-HYEONG ,  MADAN ANITA

IPC: C23C16/24 ,  C23C16/46 ,  H01L21/00 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: C23C16/24 ,  C23C16/46 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a polycrystalline silicon having hyperfine particle sizes.
SOLUTION: The method of forming a polycrystalline silicon having hyperfine particle sizes employs a differential heating of upper and lower surfaces of a substrate of a CVD apparatus, in which the lower surface of the substrate receives considerably more power than the upper surface, preferably more than 75% of the entire power; and in which the substrate is maintained during deposition at a temperature higher than 50°C above 550°C of crystallization temperature of silicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 待解决的问题：提供一种形成具有超细粒径的多晶硅的方法。 解决方案：形成具有超细粒度的多晶硅的方法采用CVD装置的基板的上表面和下表面的差加热，其中基板的下表面比上表面受到相当大的功率， 优选超过整个功率的75％; 并且其中在高于硅的结晶温度高于550℃的温度高于50℃的温度下沉积时，保持基板。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2012054555A

公开(公告)日：2012-03-15

申请号：JP2011187435

申请日：2011-08-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICKY S AMOS ,  BOYD DIANE C ,  CYRIL CABRAL JR ,  RICHARD D KAPLAN ,  JAKUB T KEDZIERSKI ,  VICTOR KU ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  ANNE L ZEUGEN ,  SERENDRA MAHESWARAN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal oxide semiconductor integration process that allows a plurality of silicide metal gates to be prepared on a gate dielectric.SOLUTION: There is provided a CMOS silicide metal gate integration method capable of eliminating a demerit of generation of variations in the height of poly Si gate stock which varies a silicide metal gate phase. The integration method minimizes the complexity of the process, thereby restraining the manufacturing cost of a CMOS transistor from increasing.

Abstract translation: 要解决的问题：提供允许在栅极电介质上制备多个硅化物金属栅极的互补金属氧化物半导体集成工艺。 解决方案：提供了一种CMOS硅化物金属栅极集成方法，其能够消除改变硅化物金属栅极相的多晶硅栅极原料的高度变化的缺点。 该集成方法最小化了工艺的复杂性，从而抑制了CMOS晶体管的制造成本增加。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：WO2007136907A2

公开(公告)日：2007-11-29

申请号：PCT/US2007063377

申请日：2007-03-06

Applicant: IBM ,  YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8W/cm 2 and 5.0W/cm 2 ; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Abstract translation: 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：WO2005083780A2

公开(公告)日：2005-09-09

申请号：PCT/US2005005565

申请日：2005-02-22

Applicant: IBM ,  AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

Inventor： AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

Abstract translation: 本发明提供了互补金属氧化物半导体集成工艺，由此在栅极电介质顶上制造多个硅化金属栅极。 不管硅化物金属栅极的尺寸如何，使用本发明的集成方案形成的每个硅化金属栅极具有相同的硅化物金属相和基本相同的高度。 本发明还提供了形成具有硅化触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。