公开(公告)号：EP1356498A4

公开(公告)日：2009-05-13

申请号：EP01990114

申请日：2001-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ENGEL BRETT H ,  HOINKIS MARK ,  MILLER JOHN A ,  SEO SOON-CHEON ,  WANG YUN-YU ,  WONG HON WONG

IPC: H01K3/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/50 ,  H01L23/52 ,  H01L23/532 ,  H05K3/02

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect (30, 50) and low-k interlayer dielectrics (40), a problem of open circuits after heat treatment was discovered and solved bz the use of a first liner layer of Cr (42), followed by a conformal liner layer of CVD TiN (46), followed in turn bz a final liner layer of Ta or TaN (48), thus improving adhesion between the via (50) and the underlying copper layer (30) while maintianing low resistance.

公开(公告)号：EP1397830A4

公开(公告)日：2009-03-11

申请号：EP01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，发现热处理后开路的问题，并通过使用Ti的第一衬垫层（42），随后使用CVD共形衬垫层（46） TiN，然后依次是TA或TaN的最终衬垫层（48），因此改善了通孔和下面的铜层之间的粘合性，同时将由Ti和铜之间的合金化引起的电阻的增加减少到可接受的量。

公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：EP1356507A4

公开(公告)日：2008-05-21

申请号：EP01996224

申请日：2001-12-30

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  BRODSKY STEPHEN BRUCE ,  CABRAL CYRIL JR ,  DOMENICUCCI ANTHONY G ,  RANSOM CRAIG MITCHELL ,  WANG YUN-YU ,  WILDMAN HORATIO S ,  WONG KWONG HON

IPC: C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44

CPC classification number: C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

Abstract: A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.

公开(公告)号：EP2095409A4

公开(公告)日：2014-05-21

申请号：EP07842115

申请日：2007-09-10

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  WANG PING-CHUAN ,  WANG YUN-YU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76847 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2033213A4

公开(公告)日：2012-08-01

申请号：EP07757974

申请日：2007-03-06

Applicant: IBM

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  B05D3/00 ,  C23C16/34 ,  C23C16/505 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

公开(公告)号：JP2004336051A

公开(公告)日：2004-11-25

申请号：JP2004136335

申请日：2004-04-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  GRECO STEPHEN E ,  KWIETNIAK KEITH T ,  SEO SOON-CHEON ,  YANG CHIH-CHAO ,  WANG YUN-YU ,  WONG KWONG H

IPC: H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a wiring layer in an integrated circuit structure.
SOLUTION: An organic insulating layer is formed, the insulating layer is patterned, a liner is accumulated on the insulating layer, the above structure is exposed in plasma, and a pore is formed in an insulating layer of an area adjacent to the liner. The liner is formed sufficiently thin so that plasma penetrates the liner and the pore is formed on the insulating layer without influencing the liner. During the plasma processing, the plasma penetrates the liner without influencing the liner. After the plasma processing, an additional liner can be accumulated. Thereafter, a conductor is accumulated and an excessive portion of the conductor is deleted from the structure. This method produces an integrated circuit structure including the organic insulating layer having a patterned structure, a liner covering the rear side of the patterned structure, and a conductor filling the patterned structure. The insulating layer includes the pore along the surface area of the insulating layer contacting to the liner, and further, the pore is only existent along the surface area contacting to the liner (where the liner is non-existent inside the pore).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在集成电路结构中形成布线层的方法。 解决方案：形成有机绝缘层，对绝缘层进行图案化，在绝缘层上积累衬垫，将上述结构暴露在等离子体中，并且在邻近的区域的绝缘层中形成孔 衬垫。 衬垫形成得足够薄，使得等离子体穿透衬垫，并且在绝缘层上形成孔而不影响衬垫。 在等离子体处理期间，等离子体渗透衬垫而不影响衬套。 在等离子体处理之后，可以累积额外的衬垫。 此后，导体被累积，导体的过多部分从结构中删除。 该方法产生包括具有图案化结构的有机绝缘层，覆盖图案化结构的后侧的衬垫和填充图案化结构的导体的集成电路结构。 绝缘层包括沿着与衬垫接触的绝缘层的表面积的孔，此外，孔沿着与衬垫接触的表面区域（其中衬里不存在于孔内）存在。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2011051015A3

公开(公告)日：2011-10-20

申请号：PCT/EP2010062579

申请日：2010-08-27

Applicant: IBM ,  IBM UK ,  WONG KEITH KWONG HON ,  GUO DECHAO ,  KWON UNOH ,  WANG YUN-YU ,  PARKS CHRISTOPHER CARR

Inventor： WONG KEITH KWONG HON ,  GUO DECHAO ,  KWON UNOH ,  WANG YUN-YU ,  PARKS CHRISTOPHER CARR

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

Abstract translation: 提供了一种形成p型半导体器件的方法，其在一个实施例中采用含铝阈值电压偏移层来产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极介电层，存在于栅极介电层上的含铝阈值电压偏移层， 以及与含铝阈值电压偏移层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区域可以形成在衬底的与其上存在栅极结构的部分相邻的衬底中。 还提供了由上述方法提供的p型半导体器件。

公开(公告)号：WO2007136907A2

公开(公告)日：2007-11-29

申请号：PCT/US2007063377

申请日：2007-03-06

Applicant: IBM ,  YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8W/cm 2 and 5.0W/cm 2 ; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Abstract translation: 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：JP2007311796A

公开(公告)日：2007-11-29

申请号：JP2007129261

申请日：2007-05-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HAINING S YANG ,  UTOMO HENRY K ,  PURTELL ROBERT J ,  WANG YUN-YU

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7845

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for forming a CMOS device having silicide to which endogenous stress is added by using a silicon-nitride-cap. SOLUTION: First, a metal layer comprising silicide metal M is formed on the S/D region of an FET, and then an S/D metal silicide layer comprising metal silicide (MSi x ) of a first phase is formed by carrying out a first annealing step. Then, a silicon-nitride layer is formed on the FET, and then a second annealing step is carried out. During the second annealing step, the phase of metal silicide is converted from the first phase (MSi x ) to a second phase (MSi y ), where x COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成具有通过使用氮化硅帽加入内应力的硅化物的CMOS器件的结构和方法。 解决方案：首先，在FET的S / D区域上形成包含硅化物金属M的金属层，然后将包含金属硅化物的S / D金属硅化物层（MSi xS / 通过进行第一退火步骤形成第一相。 然后，在FET上形成氮化硅层，然后进行第二退火工序。 在第二退火步骤期间，金属硅化物的相从第一相（MSi x ）转变为第二相（MSi y ），其中x