公开(公告)号：EP2111637A4

公开(公告)日：2012-08-08

申请号：EP08728172

申请日：2008-01-24

Applicant: IBM

Inventor： BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

IPC: H01L23/12 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/768

CPC classification number: H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

公开(公告)号：EP2033213A4

公开(公告)日：2012-08-01

申请号：EP07757974

申请日：2007-03-06

Applicant: IBM

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  B05D3/00 ,  C23C16/34 ,  C23C16/505 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

公开(公告)号：JP2011124601A

公开(公告)日：2011-06-23

申请号：JP2011024165

申请日：2011-02-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  YANG DAEWON

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/786

CPC classification number: H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a structure and method for providing mechanical stress into a CMOS structure for raising device performance and improving the yield of a chip. SOLUTION: A CMOS structure and methods for fabricating the CMOS structure are provided, wherein a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种将机械应力提供到CMOS结构中以提高器件性能并提高芯片产量的结构和方法。 提供了CMOS结构和制造CMOS结构的方法，其中位于第一晶体管之上的第一应力层和位于第二晶体管上方的第二应力层邻接但不重叠。 当在第一晶体管和第二晶体管之一内的源极/漏极区域上形成与硅化物层的接触时，这种不存在重叠的基台提供增强的制造灵活性。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007300090A

公开(公告)日：2007-11-15

申请号：JP2007106817

申请日：2007-04-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  YANG DAEWON

IPC: H01L21/8238 ,  H01L21/768 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a structure applying mechanical stress in a CMOS structure for improving device performance and the yield of chips, and a method therefor. SOLUTION: The invention relates to a CMOS structure and a method for manufacturing the CMOS structure, in which a first stressed layer arranged on a first transistor and a second stressed layer on a second transistor are contacted but are not overlapped to each other. With such contact that is not overlapped, flexibility in manufacturing is improved when forming the contact to a silicide layer on a source/a drain region in one of the first and the second transistor. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在CMOS结构中应用机械应力以提高器件性能和芯片产量的结构及其方法。 解决方案：本发明涉及CMOS结构和制造CMOS结构的方法，其中布置在第一晶体管上的第一应力层和第二晶体管上的第二应力层接触但不彼此重叠 。 通过不重叠的接触，当形成与第一和第二晶体管中的一个的源极/漏极区域上的硅化物层的接触时，制造中的柔性得到改善。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2008091985A3

公开(公告)日：2008-10-02

申请号：PCT/US2008051870

申请日：2008-01-24

Applicant: IBM ,  BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

Inventor： BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

IPC: H01L23/12

CPC classification number: H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

Abstract: A dielectric cap (100) and related methods are disclosed. In one embodiment, the dielectric cap (100) includes a dielectric material (108) having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap (100) exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

Abstract translation: 公开了一种电介质帽（100）和相关方法。 在一个实施例中，电介质帽（100）包括具有光学带隙（例如，大于约3.0电子伏特）的介电材料（108）以在固化处理期间基本上阻挡紫外辐射，并且包括具有电子供体的氮， 双键电子。 电介质帽（100）表现出高模量，并且在例如铜低k线后端（BEOL）纳米电子器件的ULK UV固化处理下稳定，导致更少的膜和器件开裂以及更高的可靠性 。

公开(公告)号：WO2007136907A2

公开(公告)日：2007-11-29

申请号：PCT/US2007063377

申请日：2007-03-06

Applicant: IBM ,  YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8W/cm 2 and 5.0W/cm 2 ; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Abstract translation: 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：SG162764A1

公开(公告)日：2010-07-29

申请号：SG2010040160

申请日：2007-11-16

Applicant: GLOBALFOUNDRIES SINGAPORE PTE ,  IBM ,  INFINEON TECHNOLOGIES AG ,  SAMSUNG

Inventor： WAY TEH YOUNG ,  XIANGDONG CHEN ,  FEN JAMIN F ,  YANG DAEWON ,  BELYANSKY MICHAEL P ,  KNOEFLER ROMAN ,  JUNG KIM JUN

Abstract: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and 5 forming an interlayer dielectric over the stress formation layer and the wafer. Fig 1

公开(公告)号：SG144034A1

公开(公告)日：2008-07-29

申请号：SG2007177991

申请日：2007-11-16

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES AG ,  SAMSUNG

Inventor： WAY TEH YOUNG ,  XIANGDONG CHEN ,  FEN JAMIN F ,  YANG DAEWON ,  BELYANSKY MICHAEL P ,  KNOEFLER ROMAN ,  JUNG KIM JUN

Abstract: INTEGRATED CIRCUIT SYSTEM HAVING STRAINED TRANSISTOR An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.