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公开(公告)号：US3740590A
公开(公告)日：1973-06-19
申请号：US3740590D
申请日：1971-12-17
Applicant: IBM
Inventor： HART R , LEININGER J
Abstract: A latch circuit in which false output and skewing of binary output signals on the latch output terminal are eliminated comprising conventional set and hold-clear logic sections. The improvement comprising logic means having an input terminal adapted for connection to the set signals and an output terminal connected to the output latch terminal and being responsive to the set signals for maintaining the state of the latch output terminal during a clock signal transition, and means for simultaneously applying binary clock signals of a first state to the set section and binary clock signals of opposite state to the hold-clear sections so as to allow one or the other to be activated.
Abstract translation: 锁存电路，其中消除了锁存器输出端子上的二进制输出信号的错误输出和偏移，包括常规的设置和保持清除逻辑部分。 该改进包括具有适于连接到设置信号的输入端子和连接到输出锁存端子的输出端子的逻辑装置，并响应于设置信号以在时钟信号转换期间保持锁存器输出端子的状态， 用于将第一状态的二进制时钟信号同时向保持清除部分施加相反状态的二进制时钟信号，以允许一个或另一个激活。
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公开(公告)号：BR7903716A
公开(公告)日：1980-02-05
申请号：BR7903716
申请日：1979-06-12
Applicant: IBM
Inventor： FAIRCHILD P , LEININGER J
Abstract: A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.
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Patent Agency Ranking
公开(公告)号：BR8003880A
公开(公告)日：1981-01-13
申请号：BR8003880
申请日：1980-06-20
Applicant: IBM
Inventor： FAIRCHILD P , LEININGER J
Abstract: A storage address link register system for enabling nested program branching wherein a first subroutine may call a second subroutine which is executed before the first subroutine returns program control back to the program which called it. The system includes a mechanism whereby the same set of storage address link registers may be used for nested branching both during the execution of a normal program and during the execution of an interrupt service program which breaks into the normal program and takes over control of the processor for a short interval of time. A mechanism is provided for saving the normal program values in the link registers at the commencement of the interrupt service program. A further mechanism is provided for monitoring the usage of the link registers by the interrupt program for enabling the normal program values to be restored in the link registers only after all interrupt program values have been removed from such link registers.
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公开(公告)号：BR8003879A
公开(公告)日：1981-01-13
申请号：BR8003879
申请日：1980-06-20
Applicant: IBM
Inventor： FAIRCHILD P , LEININGER J , BLISS F
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公开(公告)号：BR7903715A
公开(公告)日：1980-02-05
申请号：BR7903715
申请日：1979-06-12
Applicant: IBM
Inventor： LEININGER J , DIXON J
Abstract: In a data processing system, a mechanism provides independent assignment of page locations for a program's instructions and its data and better enables control to be transferred between programs, or portions thereof, that reside at different addresses in different pages of a multiple page instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return and Link instructions, each of which transfers control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.
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公开(公告)号：BR7802682A
公开(公告)日：1978-12-19
申请号：BR7802682
申请日：1978-04-28
Applicant: IBM
Inventor： AMES R , TAYLOR G , LEININGER J , HARDIN D
Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
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