公开(公告)号：EP2036130A4

公开(公告)日：2009-12-23

申请号：EP07797521

申请日：2007-05-17

Applicant: IBM

Inventor： LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

IPC: H01L29/76

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

公开(公告)号：WO2007140130A3

公开(公告)日：2009-04-09

申请号：PCT/US2007069100

申请日：2007-05-17

Applicant: IBM ,  LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

Inventor： LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

IPC: H01L29/76

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract translation: 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

公开(公告)号：SG146549A1

公开(公告)日：2008-10-30

申请号：SG2008019333

申请日：2008-03-10

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHAN VICTOR W C ,  SUNFEI FANG ,  DYER THOMAS W ,  LI JINGHONG H ,  JIANG YAN ,  UTOMO HENRY K ,  JUNG TANG TECK

Abstract: SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET Methods of forming a silicide in an embedded silicon germanium (eSiGe) source/drain region using a silicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen- containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.