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    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
    1.
    发明公开
    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
    方法形成自对准DOPPELSALIZID CMOS技术

    公开(公告)号：EP1825508A4

    公开(公告)日：2009-06-24

    申请号：EP05852638

    申请日：2005-12-01

    Applicant: IBM

    Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

    SELF-FORMING METAL SILICIDE GATE FOR CMOS DEVICES
    3.
    发明公开
    SELF-FORMING METAL SILICIDE GATE FOR CMOS DEVICES 审中-公开
    自FORM金属硅化物-GATE CMOS设备

    公开(公告)号：EP1856725A4

    公开(公告)日：2009-01-14

    申请号：EP06717971

    申请日：2006-01-10

    Applicant: IBM

    Inventor： LUO ZHIJIONG ,  FANG SUNFEI ,  ZHU HUILONG

    IPC: H01L21/336 ,  H01L29/76

    CPC classification number: H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7833

    Abstract: A process for forming a metal silicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (3) (polysilicon or amorphous silicon) is formed overlying the gate dielectric (2); a layer of metal (4) is then formed on the first layer (3), and a second layer of silicon (5) on the metal layer (4). A high-temperature (greater than 700 0C) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer (30) above the gate dielectric (2) by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer (50) from silicon in the second layer (5). The thicknesses of the layers are such that in the high-temperature processing, substantially all the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully suicided gate structure may be produced.

    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
    4.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
    在CMOS技术中形成自对准双重杀菌剂的方法

    公开(公告)号：WO2006060575A2

    公开(公告)日：2006-06-08

    申请号：PCT/US2005043474

    申请日：2005-12-01

    Applicant: IBM ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

    Abstract translation: 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

    N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME
    5.
    发明申请
    N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME 审中-公开
    包含双重压力机的N沟道MOSFET及其形成方法

    公开(公告)号：WO2007140130A3

    公开(公告)日：2009-04-09

    申请号：PCT/US2007069100

    申请日：2007-05-17

    Applicant: IBM ,  LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

    Inventor： LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

    IPC: H01L29/76

    CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

    Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

    Abstract translation: 本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。 具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。 第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。 第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。 这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

    Semiconductor structure and its type, and method (structure and method for forming multilayer embedded stressor)
    6.
    发明专利
    Semiconductor structure and its type, and method (structure and method for forming multilayer embedded stressor) 有权
    半导体结构及其类型和方法（形成多层嵌入式应力的结构与方法）

    公开(公告)号：JP2007329477A

    公开(公告)日：2007-12-20

    申请号：JP2007148947

    申请日：2007-06-05

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LUO ZHIJIONG ,  RICKY S AMOS ,  ROBEDO NIBO ,  UTOMO HENRY K

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786

    CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636

    Abstract: PROBLEM TO BE SOLVED: To provide a multilayer embedded stressor which is used in a semiconductor structure causing deformation in a device channel area and has a gradual dopant distribution structure. SOLUTION: This multilayer stressor is formed in a portion of a semiconductor structure where a source/drain area is generally positioned. This multilayer stressor comprises a first co-epitaxial semiconductor layer not doped or doped at a low concentration and a second epitaxial semiconductor layer doped at higher concentration than the first epitaxial semiconductor layer. Each of the first and second epitaxial layers has an identical lattice constant. The lattice constant differs from that of a substrate where each semiconductor layer is embedded. A structure including this multilayer embedded stressor ensures a good balance between an adjacent stress and a short channel effect and eliminates or substantially reduces any defects which generally occur during deeper source/drain area formation. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在半导体结构中使用的多层嵌入式应力器，其导致器件沟道区域的变形并且具有逐渐的掺杂剂分布结构。 解决方案：该多层应力器形成在半导体结构的一般位于源极/漏极区域的部分中。 该多层应力器包括不掺杂或以低浓度掺杂的第一外延半导体层和以比第一外延半导体层更高的浓度掺杂的第二外延半导体层。 第一和第二外延层中的每一个具有相同的晶格常数。 晶格常数不同于嵌入每个半导体层的衬底的晶格常数。 包括这种多层嵌入式应力器的结构确保相邻应力和短沟道效应之间的良好平衡，并且消除或基本上减少了在较深源/漏区形成期间通常发生的任何缺陷。 版权所有（C）2008，JPO＆INPIT

    Semiconductor device, method of forming asymmetric p/n junction for fet device, and method of forming fet device (asymmetric source/drain junction for low-power silicon-on-insulator device)
    8.
    发明专利
    Semiconductor device, method of forming asymmetric p/n junction for fet device, and method of forming fet device (asymmetric source/drain junction for low-power silicon-on-insulator device) 有权
    半导体器件，形成用于FET器件的不对称P / N结的方法和形成FET器件的方法（用于低功率硅绝缘体器件的不对称源/漏极连接）

    公开(公告)号：JP2010206185A

    公开(公告)日：2010-09-16

    申请号：JP2010016896

    申请日：2010-01-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LUO ZHIJIONG ,  ZHU HUILONG ,  KIM SEONG-DONG

    IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336

    CPC classification number: H01L21/26586 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having asymmetric p/n junctions.
    SOLUTION: The semiconductor device includes an embedded insulator layer formed on a bulk substrate; a first type semiconductor material formed on the embedded insulator layer and corresponding to a body region of a field-effect transistor (FET); a second type semiconductor material, formed over the embedded insulator layer so as to be adjacent to the mutually opposing sides of the body region, corresponding to source and drain regions of the FET device, and having a bandgap which differs from that of the first type semiconductor material, wherein a source-side p/n junction of the FET is located mostly within either the first or the second type of semiconductor materials having a narrower bandgap; and a drain-side p/n junction of the FET is located within either the first or the second type semiconductor materials which have a wider bandgap.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有不对称p / n结的半导体器件。 解决方案：半导体器件包括形成在本体衬底上的嵌入式绝缘体层; 形成在所述嵌入绝缘体层上并对应于场效应晶体管（FET）的体区的第一类型半导体材料; 第二类型半导体材料，其形成在所述嵌入式绝缘体层上以与所述FET器件的源极和漏极区域相对应的与所述体区域的相对的相对侧相邻并且具有与所述第一类型的不同的带隙 半导体材料，其中FET的源极p / n结大部分位于具有较窄带隙的第一或第二类型的半导体材料之中; 并且FET的漏极侧p / n结位于具有更宽带隙的第一或第二类型半导体材料中。 版权所有（C）2010，JPO＆INPIT

    Finfet structure with multiply stressed gate electrode
    9.
    发明专利
    Finfet structure with multiply stressed gate electrode 有权
    具有多重应力门电极的FINFET结构

    公开(公告)号：JP2007158329A

    公开(公告)日：2007-06-21

    申请号：JP2006317780

    申请日：2006-11-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ZHU HUILONG ,  LUO ZHIJIONG

    IPC: H01L29/786 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/7842

    Abstract: PROBLEM TO BE SOLVED: To provide a finFET structure with enhanced performance and a method of producing the finFET structure.
    SOLUTION: A semiconductor structure and its producing method include a semiconductor fin located on a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different from the first stress in a second region located farther from the semiconductor fin. The semiconductor fin may also be positioned so that it is placed on a pedestal within the substrate. The semiconductor structure is annealed under desirable stress conditions to enhance the performance of the semiconductor device.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有增强性能的finFET结构和制造finFET结构的方法。 解决方案：半导体结构及其制造方法包括位于基板上的半导体翅片。 栅电极位于半导体鳍上方。 栅电极在位于更靠近半导体鳍片的第一区域中具有第一应力，并且在远离半导体鳍片的第二区域中具有与第一应力不同的第二应力。 半导体鳍片也可以被定位成使得它被放置在衬底内的基座上。 半导体结构在期望的应力条件下退火以提高半导体器件的性能。 版权所有（C）2007，JPO＆INPIT

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