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    2.
    发明专利
    未知

    公开(公告)号：BR8903449A

    公开(公告)日：1990-03-06

    申请号：BR8903449

    申请日：1989-07-13

    Applicant: IBM

    Inventor： BURGHARTZ JOACHIM NORBERT ,  GINSBERG BARRY JACK ,  MADER SIEGFRIED R

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L21/20 ,  H01L21/306 ,  H01L29/70

    Abstract: Bipolar transistors having self-aligned emitter-base regions and a method of forming such transistors using selective and non-selective epitaxy are disclosed. A substrate (12) of semiconductor material of a first conductivity type, a portion of which forms a collector region is provided. A first layer (18) of semiconductor material of a second conductivity type is deposited on said substrate, a portion of which forms an intrinsic base region. Over a portion of said first layer (18) an element (30) of insulating material is formed. Said intrinsic base region is formed below said element (30) and the remainder of said first layer forms an extrinsic base region. A second layer (32) of semiconductor material of said second conductivity type is deposited on said first layer (18). A portion of said second layer laterally overgrows onto a portion of an upper surface (33) of said element (30) defining an aperture (29) and leaving an exposed region (31) on the upper surface (33). The second layer (32) forms a portion of the extrinsic base region. On said second layer (32) a layer (42) of insulating material is formed which narrows said aperture (29) and said exposed region (31) of said element (30). Said narrowed exposed region (31) of said element (30) is removed to expose a portion (50) of said first layer (21) below said aperture (29) and an emitter region (54) of said first conductivity type is formed in said first layer (21) through said aperture (44).

    BIPOLAR TRANSISTOR HAVING SELF-ALIGNED EMITTER-BASE AND METHOD OF FORMING SAME USING SELECTIVE AND NON-SELECTIVE EPITAXY
    4.
    发明专利
    BIPOLAR TRANSISTOR HAVING SELF-ALIGNED EMITTER-BASE AND METHOD OF FORMING SAME USING SELECTIVE AND NON-SELECTIVE EPITAXY 未知

    公开(公告)号：CA1311859C

    公开(公告)日：1992-12-22

    申请号：CA601601

    申请日：1989-06-02

    Applicant: IBM

    Inventor： BURGHARTZ JOACHIM N ,  GINSBERG BARRY J ,  MADER SIEGFRIED R

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L21/20 ,  H01L29/72

    Abstract: BIPOLAR TRANSISTOR HAVING SELF-ALIGNED EMITTER-BASE AND METHOD OF FORMING SAME USING SELECTIVE AND NON-SELECTIVE EPITAXY Selective and non-selective epitaxial growth is utilized to form a bipolar transistor having self-aligned emitter and base regions. A substrate of semiconductor material of a first conductivity type is provided and a first layer of semiconductor material of a second conductivity type is non-selectively epitaxially grown on the substrate. An insulating element is formed on a portion of the first layer of semiconductor material and a second layer of semiconductor material of the second conductivity type is selectively epitaxially grown on the first layer such that a portion of the second layer laterally overgrows onto an upper surface of the insulating element. The lateral overgrowth forms an aperture in the second layer to expose a region of the upper surface of insulating element, A layer of insulating material is formed on the accond layer to isolate the second layer of semiconductor material from a subsequent deposition of conductive material. The portion of the insulating layer formed within the aperture narrows the aperture and the exposed region of the element. The exposed region of the element is removed to expose a portion of the first layer and an emitter region of the first conductivity type is formed in the first layer through the aperture. Y0988-038

    FORMING SILICON INTEGRATED CIRCUIT REGION BY THE IMPLANTATION OF ARSENIC AND GERMANIUM
    5.
    发明专利
    FORMING SILICON INTEGRATED CIRCUIT REGION BY THE IMPLANTATION OF ARSENIC AND GERMANIUM 未知

    公开(公告)号：CA1075831A

    公开(公告)日：1980-04-15

    申请号：CA287340

    申请日：1977-09-23

    Applicant: IBM

    Inventor： MADER SIEGFRIED R ,  MASTERS BURTON J ,  POGGE HANS B

    IPC: H01L21/265 ,  H01L29/167 ,  H01L21/24

    Abstract: FORMING SILICON INTEGRATED CIRCUIT REGION BY THE IMPLANTATION OF ARSENIC AND GERMANIUM A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom -2 concentration of at least 1 x 10 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5.delta. smaller -- when high arsenic atom concentra -2 tions of at least 1 x 10 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.

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