Abstract:
A method of fabricating high-speed planar transistor structures by reducing carrier lifetime through doping with carrier lifetime killers. Gold is diffused through the front surface of the silicon structure during transistor fabrication. The gold is introduced from the vapor phase in a controlled manner so that its solid solubility in silicon is not exceeded. A simultaneous gold and base diffusion is preferred. Such a simultaneous diffusion produces a novel planar transistor structure having a gold distribution curve with an unexpected increased concentration peak in the region proximate to the basecollector junction.
Abstract:
A method for producing integrated circuit resistors of relatively high resistivity which are temperature stable, i.e., have a low temperature coefficient of resistance at operating temperatures. The resistor is formed in a selected region of an integrated circuit substrate through the introduction of appropriate dopant ions by standard ion implantation or diffusion techniques. However, the concentration of such introduced dopant ions is in excess of the concentration ordinarily required by such techniques. The region into which such dopant ions are introduced is subjected to a bombardment with non-dopant ions at a dose which is sufficient to damage the crystal structure of the region but insufficient to form an amorphous phase in this bombarded region; the bombardment may be carried out either before, after or, where appropriate, even simultaneously with the introduction of the dopant ions. As a result of this ion bombardment, the sheet resistance of the resistor region becomes substantially higher than the selected resistance despite the presence of excess dopant ions. Then, the substrate is heated at a temperature of from 500*C. to 800*C. for a time sufficient to partially anneal the damage so as to lower the sheet resistance of the region to the selected sheet resistance. The annealing time/temperature cycle is carried out so as to maintain the temperature coefficient of resistance below the temperature coefficient of resistance for conventional high resistivity resistors produced by ion implantation or diffusion.
Abstract:
FORMING SILICON INTEGRATED CIRCUIT REGION BY THE IMPLANTATION OF ARSENIC AND GERMANIUM A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom -2 concentration of at least 1 x 10 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5.delta. smaller -- when high arsenic atom concentra -2 tions of at least 1 x 10 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.
Abstract:
A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.
Abstract:
A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.
Abstract:
A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.